Hi Tim! Would you please join us on Sundsay 9pm HKT? Because I think we first have to measure out the actual properties of what we are actuall building here, before we can do predictions on these details. But I'm eager to hear your take on that!
Cheers David
On Saturday, 10 March 2018 4:08:23 AM HKT Tim Edwards wrote:
Hello David,
I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers.
Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers?
I would think that you would want diodes, especially ESD structure diodes, and vertical bipolars to test latchup conditions, and maybe some lateral bipolars as well to see what the beta is.
And I agree with Staf that you will want to push the design rules, e.g., long metal, poly, and diffusion strips at close spacing to get a statistical distribution of how often they end up shorting.
Also long thin poly strips to get a statistical distribution of spot defects large enough to cause an open.
---Tim+--------------------------------+-------------------------------------+
| R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 |
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