[Libre-silicon-devel] PAD Cells

Hello List!

While doing some homework regarding our PAD cells, I once again looked into the MOSIC Design Rules for Scalable CMOS [0].

Out of Rule Set 10.x we get the mimimum grid for bonding pad areas with 102 micron.

So my question is here, do somebody has access to bonding machines and their documentation and can provide the grid of bonding pad areas this machines usually can handle?

Is this 95u/100u as I still remember? Or are this machines already in the milli-inch-measured domain, e.g. 4 mil for 101.6u?

Curious, Hagen.

[0] https://www.mosis.com/files/scmos/scmos.pdf