Hello list!
On 06/28/2018 08:34 AM, David Lanzendörfer wrote:
Now I've got everything under control, next is to add the FPGA top levels back and allow people to choose whether they wanna build an ASIC or for an FPGA. I guess I should have a README done until tonight, ok?
BTW, there is a Best-Practise style of switching between ASIC and FPGA targets. Let's explain
1. On ASICs there has to have a RESET for every register (Latch, FlipFlop). But on FPGA RESETs are useless (you can re-config the whole FPGA instead). While without a global line (aka RESET) which goes everywhere, the timing (and working frequency) gets better results.
2. With configuration, every register gets a initial value, so use them instead of RESET.
Example code (in Verilog)
// --------------------------------------------------------------
localparam c_register_reset = 0; // 1st, define reset value `ifdef CODINGSTYLE_FPGA reg [31:0] r_register = c_register_reset; // assign initial value `else // ASIC-like reg [31:0] r_register; // for ASIC w/o initial value `endif
`ifdef CODINGSTYLE_FPGA always @ (posedge clk) begin `else always @ (posedge rst or posedge clk) begin if (rst) r_register <= c_register_reset; // reset value for ASICs only else `endif // operational with posedge clock // ... end
// ---------------------------------------------------------------
Usually, I put the CODINGSTYLE_FPGA into my Makefile environment to switch between both targets.
Regards, Hagen Sankowski