27 Jun
2018
27 Jun
'18
8:41 p.m.
On Wed, Jun 27, 2018 at 8:28 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hi all I've now managed to strip away the Xilinx/FPGA specific configuration quirks
ah i need those, for testing on a ZC706.
and only produce a plain Verilog core which is platform agnostic: https://github.com/libresilicon/SauMauPing1/tree/master/builds Next steps are:
- Wire all the peripherals out
david do you have someone who can write a priority muxer, in chisel3? the IOF code by SiFive can't cope with the many-pins-to-one-input case and i'd like chisel3 to be one of the back-ends for the libre pinmux code-generator.
l.