27 Jun
2018
27 Jun
'18
8:18 p.m.
Hello David, Is it possible for you to add a README file for how to use it? Best regards, Manili
On Jun 27, 2018, at 11:58 PM, David Lanzendörfer <david.lanzendoerfer@o2s.ch> wrote:
Hi all I've now managed to strip away the Xilinx/FPGA specific configuration quirks and only produce a plain Verilog core which is platform agnostic: https://github.com/libresilicon/SauMauPing1/tree/master/builds Next steps are: * Wire all the peripherals out * Wire a GPU in there.
For the GPU I'd prefer either Verilog (because of the Yosys support) or Chisel/Scala (Generates Verilog)
Cheers -lev