On Wed, Jan 23, 2019 at 10:05 PM Hagen SANKOWSKI hsank@posteo.de wrote:
Last May we did our 1st LibreSilicon Hackathon to evaluate all the tools and formats, which could be interesting for us.
Well, I like to re-post the Outcome here again
https://hackmd.c3d2.de/libresiliconThe site is in German and should be almost complete.
As I have some time to think, I wonder: Has any of you done an actual analog IC design, comprising * (parametric) cell definition * schematic capture * schematic simulation (corners? Monte Carlo??) * layout (schematic driven? manual??) * Layout DRC * LvS * layout parasitic extraction * post layout simulation * streamout (to CIF? to GDS??) with any of these tool chains?
In the meantime, I'm trying to get academic local access to Cadence, so that I can separate the task of designing proof-of-concept analog circuits from developing and maturing a tool chain.
Gruß aus Berlin tatzelbrumm