Op 21/07/2021 om 22:54 schreef David Lanzendörfer:
Hi Staf Ok. That was, what I had asked TSMC among other things in my email, so thanks for answering this question. I don't really care who and how. All I wanna do is generate a layout, which I place and route and revision control on my public Git repository and I want a foundry which tapes it out.
With some delay I am now starting on preparing for the beta tape-out on TSMC 0.35um. Timeline: first design available in two weeks (Oct. 10th) and a final version one month from now (Oct. 29th). Payment should be done by Nov. 8th. Cost will likely by €1750 unless we see that your design is too big; to be worked in detail when we go along. Sorry for late notice. I think it is best to start now already the discussion by detailing a little more what you want to tape-out if you agree to the offer. I should be able to handle a GDSII that is DRC clean for the 0.35um SCMOS design rules; more precisely SCN4M_SUBM with lambda of 0.20. AFAIK this should be available in magic. I am working on MOSIS 0.35 SCMOS rules support for klayout. Time of arrival for the latter is unknown though; as I am currently a little bit overstretched.
BTW: I did see that IMEC now works with you without even bothering to come back to me concerning my question whether it would be possible to at least give us access to some design rules, so that we can generate standard cells with them. If you could get us some design rules for IMEC, we could start generating standard cells and synthesize some test chips for this process... THAT would be interesting.
Sorry for not replying earlier but imec is only allowed to give anything coming from TSMC to customers who have signed the three-way NDA between the customer, imec and TSMC. TSMC will only agree to a new NDA after telling them the product you are working on and evaluation of your market potential. Also for imec these older nodes have too much overhead compared to possible financial benefit so they are mainly for existing users only. I have worked at imec so have personal connections there plus I was already 0.35um customer before this 'existing customers only' policy was put in place.
The three-way NDA I have signed does not allow me to distribute the design rules or any process related information that is not already public so we'll have to work with SCMOS design rules. Another service I plan to offer is that I will deliver ASICs for RTL (nmigen, VHDL, Verilog, ...) you provide to me. The NDA does forbid me to distribute the final GDSII in the TSMC design rules though.
In interest of full disclosure I want to mention I am also developing an own standard cell library. Given that I have signed the NDA I can make it conforming to these and thus be more efficient than ones that use the SCMOS rules; e.g. yours. Also, as I am working on an EDA flow fully done in python so I also don't see much collaboration potential with your work on standard cells.
greets, Staf.