This is also to ask what is the role of `icarus verilog` in a `qflow`-based workflow and when a designer wishes to use it and what is a common reasoning for that.
On Tue, May 29, 2018 at 02:34:59PM +0000, Andreas Westerwick wrote:
Hello List,
this question comes in two parts and is for hardware designers:
In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow?
The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow.
Kind regards, Andreas Westerwick