Hello List,
this question comes in two parts and is for hardware designers:
In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow?
The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow.
Kind regards, Andreas Westerwick
This is also to ask what is the role of `icarus verilog` in a `qflow`-based workflow and when a designer wishes to use it and what is a common reasoning for that.
On Tue, May 29, 2018 at 02:34:59PM +0000, Andreas Westerwick wrote:
Hello List,
this question comes in two parts and is for hardware designers:
In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow?
The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow.
Kind regards, Andreas Westerwick
Hello Andreas,
This is also to ask what is the role of `icarus verilog` in a `qflow`-based workflow and when a designer wishes to use it and what is a common reasoning for that.
Normally a digital flow would not use ng-spice, although qflow is able to make an efficient ng-spice simulation through the use of "xspice", and generates an xspice netlist.
I'm not sure what is the point of running simulations during a digital flow. I guess if you have a testbench that generates an output that can be parsed to determine if the simulation passes or fails, then you can run a simulation after any digital flow step that modifies the netlist to make sure that the modification has not caused the simulation to fail.
When running qflow, I normally run a simulation on the final netlist to make sure it works, but as I don't have any specific definition for a pass/fail testbench, qflow does not do this automatically.
---Tim
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Hi Andy
this question comes in two parts and is for hardware designers:
Ok
In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow?
Simulation on the digital level (RTL) is being done using iVerilog from Icarus verilog. For VHDL there is ghdl which does the same.
The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow.
Well. As soon as you've got the netlist done (no place and route) you can already do an STA based on the behavior VHDL/Verilog models provided for the various logic cells. That's what Hagen is doing here, he defines the theoretical timing: https://github.com/chipforge/StdCellLib/tree/master/Simulation/verilog The actual timing will then be determined in the lab actually, where we will measure out our logic cells and determine worst case and best case behavior. Respectively we can also do SPICE simulations on the transistor/wire-level (analog) and make pretty good predictions of speed-drifts based on temperature and so on. We will have to decide in a Mumble session on how we wanna get these values.
Cheers David
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Andreas Westerwick -
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Tim Edwards