Someone successfully hooked up an Atmega MCU without differential gates (and so) to a DDR interface and got the DRAM chip to do something useful. You can also just use two IO pins instead of a differential gate, you just have to keep the transfer rates low enough, then you don't even need to tinker around with pull up and pull down resistors for compensating for the I/O pad resistance :-)

Cheers -lev

On Tuesday, July 20, 2021 9:18:35 AM WEST Hagen SANKOWSKI wrote:

Hello David.

Long time ago, I had to connect an Altera FPGA with a DDR2 RAM. It was a mess, do to an on-chip bug :-(

BTW, as I still remember, at least a couple of signals are differential, eg. Clock (CKx) and Data Select (DQSx), and needing balanced routing..

Sorry. Hagen.

---

"They who can give up essential liberty to obtain a little temporary safety, deserve neither liberty nor safety." Benjamin Franklin (1775)

Am 19.07.2021 16:06 schrieb David Lanzendörfer:

...

DRAM DDR3 without leveling IS an option. We don't need special pads and can just use the I/O pads :-)

https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/ an/ an520.pdf

There we go! =^_^=~~~~~

On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote:

...

Meeting Minutes of the Mumble session today

Participants: Devon, tatzelbrumm (partly), hsank, leviathan

Topics

• (external) RAM

While thinking about an RISC-V CPU demonstrator, we need memory for loading an Operating System like Linux.

Our first guess was for the demonstrator just to use external RAM chips, e.g. with HyperRAM, which has a quite simple interface and can be driven without LVDS-IO-Pads (which are still not available for us). Unfortunately using a couple of them gets fast quite expansive.

Using commercial available (and cheaper) DRAM nowadays is out of reach for us - this chips using a proprietary interface called DDR2 or DDR3. This interface needs differential IO-Pads (the LVDS we already mentioned above) and is critical about timing (in the meaning of different wire length, wire resistance and so on).

Without a PDK for a technology we can not design the analog stuff inside 'cause we still miss all the concrete values for the layers to calculate transistor and wire sizes.

• alternative: internal hand-crafted RAM-cells

Designing internal RAM cells, no matter whether dynamic RAM or static RAM isn't possible without the analog values from the PDK..

• possible pathes to go

• Reducing the Operating System to smaller memory footprints (e.g.

with NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU

• Getting a PDK and design with a couple of iterations in silicon our

analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works..

'''' Note: if we'd start with an alien PDK we had to re-design the analog stuff from ground up again for our LibreSilicon PDK again.. ''''

If you have some suggestions how to get out of our chicken-and-egg-Problem, please drop us an email :-)

Regards, Hagen _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developersH