Hello Andreas.

On 05/29/2018 04:34 PM, Andreas Westerwick wrote:

Hello List,

this question comes in two parts and is for hardware designers:

In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically.

I do not see the reason for doing the simulation *after* *each* step in the workflow.

Before getting the netlist, you do intensiv simulations for verifying your design. Afterwards, with place and route already done, the STA checks, that your design still meets the timing requirements.

As Tim mentioned, you probably could verify that your design is still sane after place and route - with self-checking testbenches. Seriously, only a minority of designers can write good / sophisticated testbenches.

So my guess here is, that the tool flow in Alliance misses something like a equivalence checking tool - before and after one processing step. That would be fine to have a EQ check. I am not sure, but I think I heard something in that direction from Clifford, that Yosys could do that.

Let put us the Equivalence Check on the check-list for QtFlow. Because if their are processing steps, which could be risky, or you would still not trust the fresh developed tools - a EQ check can recognize whether the design is still logcial/functional the same as it was before the processing step.

Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow?

Definitely not.

And just for the record - analog simulations in spice (or ng-spice) are very time and memory consuming. Yoo wouldn't do them without a good reason.

If we starting with digital design, pure digital simulations in Verilog e.g. with Icarus Verilog, are quite faster. Analog simulations I would start, if I like so-called Mixed-Signal-Simulation with analog-parts (e.g. a ADC, DAC, or PLL is involved) and digital control logic coupled to them.

The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct?

STA tools are checking, whether the design - from a perspective of timing - still reaches the timing requirements. While with placement there is not a trustworthy source of timing information, the STA becomes useful after the Routing step. With routing, the wires gets there delay.

I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow.

Me too.

Hagen.