Hi everyone,

Hooray, we made a tapeout with Libresilicon technology!

The story starts a long time ago (around 2019) with the idea of growing standard cells from a single Inverter to a whole standard cell library like popcorn, but in a reproducible way. We developed a toolchain which starts from the Design-Rules (DRC) and netlists, and automatically layout, DRC-fix, simulate, characterize and document standard cells for each of the given netlists. That toolchain is currently able to layout about 80% of the cells DRC clean: https://github.com/thesourcerer8/StdCellLib/ You can see a resulting standard cell library here: https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.ht...

Now that the toolchain has matured enough to be usable, I decided to try it on the Skywater 130nm process node through a Google Shuttle: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project It automatically takes all the DRC-cleanly generated standard cells from StdCellLib, and puts each of the cells seperately on a test-wafer, and connects each cell up to the IO and to the internal logic analyzer (since there aren't enough IOs), then it uses OpenLane/OpenROAD to automatically layout the whole core. The whole toolchain from DRC+Netlists to test-wafer GDS runs in about 2-3 hours at the moment. I successfully submitted the design to EFabless/Google/Skywater, and expect packaged silicon back by the end of the year.

One interesting tool I developed is a generic automatic DRC fixing engine, which is used to post-process the layouted cells for more complex rules which wouldnt make sense to implement in the layout generator engine.

Open Tasks where help is needed: * I started working on automated Verification firmware that tests all possible input combinations of all the cells, but this isn't completed yet. * We should try to improve lclayout to be capable to characterize sequential cells * I implemented various workarounds (fixup's) that fix up the layout of the standard cells to be compatible with the existing Skywater standard cells. We should think about which of those should be put into lclayout, to cleanup the toolchain there. * As a next step we should take some medium complexity digital logic and completely synthesize/place/router it as a core with our own cells. Does anyone want to lead that project?

Best regards, Philipp Gühring