hi,
are there any tools that will take verilog and generate something akin to a PCB "component" plus show a set of "unrouted nets"?
i would like to get a visual feel for what a design looks like, and a conversion of verilog to "blocks" is the easiest way i can think of.
l.
Hi In order to accomplish what you described you would require a Liberty file of the 74HC logic blocks or so (e.g. 7408,7432,7400,7402,...). Then you could essentially synthesize your Verilog using standard logic gates in Yosys. Then you could convert your resulting BLIF file into a KiCAD netlist and load it within KiCADs PCB layout tool. There you can then map it to standard footprints, place and route it and make a PCB out of it which you can then manufacture and pick&place assemble.
Cheers David
On Monday, 26 November 2018 5:47:43 PM HKT Luke Kenneth Casson Leighton wrote:
hi,
are there any tools that will take verilog and generate something akin to a PCB "component" plus show a set of "unrouted nets"?
i would like to get a visual feel for what a design looks like, and a conversion of verilog to "blocks" is the easiest way i can think of.
l.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Nov 26, 2018 at 10:24 AM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hi In order to accomplish what you described you would require a Liberty file of the 74HC logic blocks or so (e.g. 7408,7432,7400,7402,...). Then you could essentially synthesize your Verilog using standard logic gates in Yosys.
found a tutorial on that.
Then you could convert your resulting BLIF file into a KiCAD netlist
haven't found anything relevant under google search "blif to kicad"
and load it within KiCADs PCB layout tool.
got that installed...
There you can then map it to standard footprints, place and route it and make a PCB out of it which you can then manufacture and pick&place assemble.
i just need the visualisation part :)
l.
ah ha! i discovered yosys "show", which converts to graphviz dot-format. good enough.
yosys> read_verilog file.v yosys> show
coooool
l.
Oh. Okey. Well. Andreas is working on something similar: https://murmur.libresilicon.com/lsc/rocket-chip-yosys
Also, yeah, making a schematics out of verilog is a bit tricky, because you've gotta place the parts from the graph in the schematics and draw the wires without it becoming a total mess. But when graphviz is satisfying anyway, I'm happy :-)
Cheers David
On Monday, 26 November 2018 7:03:00 PM HKT Luke Kenneth Casson Leighton wrote:
ah ha! i discovered yosys "show", which converts to graphviz dot-format. good enough.
yosys> read_verilog file.v yosys> show
coooool
l.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Nov 26, 2018 at 11:53 AM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Oh. Okey. Well. Andreas is working on something similar: https://murmur.libresilicon.com/lsc/rocket-chip-yosys
neat!
Also, yeah, making a schematics out of verilog is a bit tricky, because you've gotta place the parts from the graph in the schematics and draw the wires without it becoming a total mess.
well, the point is: if it's a mess, that's indicative that the subdivisions and data connections in the verilog file are not good enough. it means, "break file down into smaller modules" and "Get S*** Together" :)
But when graphviz is satisfying anyway, I'm happy :-)
:)
l.
Hi
well, the point is: if it's a mess, that's indicative that the subdivisions and data connections in the verilog file are not good enough. it means, "break file down into smaller modules" and "Get S*** Together"
It's more that 32 bit buses are a bit of a mess when not using the bus wire from KiCAD Schematics. And also graph node placing has its own algorithmic theory.
Andreas did a really good job ex-lining too big subcells and grouping them in a fashion which allows to place and route subcells which have an acceptable delay because the amount of asynchronous parts within the clock domains are being reduced. Smaller propagation delay means higher frequencies.
Cheers David
On Mon, Nov 26, 2018 at 1:45 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hi
well, the point is: if it's a mess, that's indicative that the subdivisions and data connections in the verilog file are not good enough. it means, "break file down into smaller modules" and "Get S*** Together"
It's more that 32 bit buses are a bit of a mess when not using the bus wire from KiCAD Schematics. And also graph node placing has its own algorithmic theory.
Andreas did a really good job ex-lining too big subcells and grouping them in a fashion which allows to place and route subcells which have an acceptable delay because the amount of asynchronous parts within the clock domains are being reduced.
that's precisely why i want the visualisation. graphviz will do for now. i still haven't found the tool which converts BLIF to KiCAD netlist: do you have a link?
l.
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