Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC
Hello List! This is our weekly announcement for the next Mumble Sessions on Sunday 2021-07-18 @ 18:00 UTC. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. We like to follow-up our topics from mumble sessions before. Regards, Hagen.
Hi So today we've been talking about ways around having to use DDR3/DDR4 interfaces for external memory of a potential SoC but as it turns outs, all our candidates like HyperRAM or MRAM are out of the window because of the prices. As usual I came back to the question "is it possible to do this with an AVR?" which usually helps me at fixing such problems and I came across those projects here: https://www.circuitlake.com/interfacing-dram-memory-with-avr.html https://github.com/jnk0le/AVR-DRAM Turns out that it's possible to speak to DRAM over a DDR3 without a special controller, just over GPIO. They got an Atmega to access a Hitatchi M5M44800. The RAM access will be slow, but we don't need to know about the analog properties of the process in order to achieve this. I will probably implement this for my test SoC on a CPLD. Hagen will explain more in the follow up/minutes. Cheers -lev On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote:
Hello List!
This is our weekly announcement for the next Mumble Sessions on Sunday
2021-07-18 @ 18:00 UTC.
Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC.
We like to follow-up our topics from mumble sessions before.
Regards, Hagen. _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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No, bit banging with ram, no way! I had enough problems with a company whiche used gpio bit banging with a dsp )to read a fast ADC (What you dont fetch gets overwrittwn.) I On July 18, 2021 9:39:53 PM GMT+02:00, "David Lanzendörfer" <leviathan@libresilicon.com> wrote:
Hi So today we've been talking about ways around having to use DDR3/DDR4 interfaces for external memory of a potential SoC but as it turns outs, all our candidates like HyperRAM or MRAM are out of the window because of the prices. As usual I came back to the question "is it possible to do this with an AVR?" which usually helps me at fixing such problems and I came across those projects here: https://www.circuitlake.com/interfacing-dram-memory-with-avr.html https://github.com/jnk0le/AVR-DRAM Turns out that it's possible to speak to DRAM over a DDR3 without a special controller, just over GPIO. They got an Atmega to access a Hitatchi M5M44800. The RAM access will be slow, but we don't need to know about the analog properties of the process in order to achieve this. I will probably implement this for my test SoC on a CPLD. Hagen will explain more in the follow up/minutes.
Cheers -lev
On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote:
Hello List!
This is our weekly announcement for the next Mumble Sessions on Sunday
2021-07-18 @ 18:00 UTC.
Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC.
We like to follow-up our topics from mumble sessions before.
Regards, Hagen. _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com
https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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This isn't a problem with DRAM, it delivers values after you wrote the address and toggled the right bits and as long as you don't change anything, the DRAM has no reason to do something else, so I think I give hooking up some DDR3 RAM to an ICE40 a try :-) On Monday, July 19, 2021 4:49:00 PM WEST Ludwig Jaffe wrote:
No, bit banging with ram, no way! I had enough problems with a company whiche used gpio bit banging with a dsp )to read a fast ADC (What you dont fetch gets overwrittwn.)
I
On July 18, 2021 9:39:53 PM GMT+02:00, "David Lanzendörfer" <leviathan@libresilicon.com> wrote:
Hi So today we've been talking about ways around having to use DDR3/DDR4 interfaces for external memory of a potential SoC but as it turns outs, all our candidates like HyperRAM or MRAM are out of the window because of the prices. As usual I came back to the question "is it possible to do this with an AVR?" which usually helps me at fixing such problems and I came across those projects here: https://www.circuitlake.com/interfacing-dram-memory-with-avr.html https://github.com/jnk0le/AVR-DRAM Turns out that it's possible to speak to DRAM over a DDR3 without a special controller, just over GPIO. They got an Atmega to access a Hitatchi M5M44800. The RAM access will be slow, but we don't need to know about the analog properties of the process in order to achieve this. I will probably implement this for my test SoC on a CPLD. Hagen will explain more in the follow up/minutes.
Cheers -lev
On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote:
Hello List!
This is our weekly announcement for the next Mumble Sessions on
Sunday
2021-07-18 @ 18:00 UTC.
Please join us as usual at our Mumble Server murmur.libresilicon.com
at
Port 64738, the Channel is IC.
We like to follow-up our topics from mumble sessions before.
Regards, Hagen. _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com
https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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Meeting Minutes of the Mumble session today =========================================== Participants: Devon, tatzelbrumm (partly), hsank, leviathan Topics ------ - (external) RAM While thinking about an RISC-V CPU demonstrator, we need memory for loading an Operating System like Linux. Our first guess was for the demonstrator just to use external RAM chips, e.g. with HyperRAM, which has a quite simple interface and can be driven without LVDS-IO-Pads (which are still not available for us). Unfortunately using a couple of them gets fast quite expansive. Using commercial available (and cheaper) DRAM nowadays is out of reach for us - this chips using a proprietary interface called DDR2 or DDR3. This interface needs differential IO-Pads (the LVDS we already mentioned above) and is critical about timing (in the meaning of different wire length, wire resistance and so on). Without a PDK for a technology we can not design the analog stuff inside 'cause we still miss all the concrete values for the layers to calculate transistor and wire sizes. - alternative: internal hand-crafted RAM-cells Designing internal RAM cells, no matter whether dynamic RAM or static RAM isn't possible without the analog values from the PDK.. - possible pathes to go * Reducing the Operating System to smaller memory footprints (e.g. with NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU * Getting a PDK and design with a couple of iterations in silicon our analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works.. '''' Note: if we'd start with an alien PDK we had to re-design the analog stuff from ground up again for our LibreSilicon PDK again.. '''' If you have some suggestions how to get out of our chicken-and-egg-Problem, please drop us an email :-) Regards, Hagen
Hi I've been thinking about this Atmega project which communicated with a DDR3 chip using GPIOs. I think I'm going to try this out with an FPGA. The data transfer rate will probably be terrible, but it seems to be an option. Opinions? Cheers -lev On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote:
Meeting Minutes of the Mumble session today ===========================================
Participants: Devon, tatzelbrumm (partly), hsank, leviathan
Topics ------
- (external) RAM
While thinking about an RISC-V CPU demonstrator, we need memory for loading an Operating System like Linux.
Our first guess was for the demonstrator just to use external RAM chips, e.g. with HyperRAM, which has a quite simple interface and can be driven without LVDS-IO-Pads (which are still not available for us). Unfortunately using a couple of them gets fast quite expansive.
Using commercial available (and cheaper) DRAM nowadays is out of reach for us - this chips using a proprietary interface called DDR2 or DDR3. This interface needs differential IO-Pads (the LVDS we already mentioned above) and is critical about timing (in the meaning of different wire length, wire resistance and so on).
Without a PDK for a technology we can not design the analog stuff inside 'cause we still miss all the concrete values for the layers to calculate transistor and wire sizes.
- alternative: internal hand-crafted RAM-cells
Designing internal RAM cells, no matter whether dynamic RAM or static RAM isn't possible without the analog values from the PDK..
- possible pathes to go
* Reducing the Operating System to smaller memory footprints (e.g. with NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU
* Getting a PDK and design with a couple of iterations in silicon our analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works..
'''' Note: if we'd start with an alien PDK we had to re-design the analog stuff from ground up again for our LibreSilicon PDK again.. ''''
If you have some suggestions how to get out of our chicken-and-egg-Problem, please drop us an email :-)
Regards, Hagen _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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Hi I just came across this IP core, which apparently can talk to normal DDR3 RAM without a special type of pads or controller... https://opencores.org/projects/ddr3_sdram I think I'll gonna try it :-) Cheers -lev On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote:
Meeting Minutes of the Mumble session today ===========================================
Participants: Devon, tatzelbrumm (partly), hsank, leviathan
Topics ------
- (external) RAM
While thinking about an RISC-V CPU demonstrator, we need memory for loading an Operating System like Linux.
Our first guess was for the demonstrator just to use external RAM chips, e.g. with HyperRAM, which has a quite simple interface and can be driven without LVDS-IO-Pads (which are still not available for us). Unfortunately using a couple of them gets fast quite expansive.
Using commercial available (and cheaper) DRAM nowadays is out of reach for us - this chips using a proprietary interface called DDR2 or DDR3. This interface needs differential IO-Pads (the LVDS we already mentioned above) and is critical about timing (in the meaning of different wire length, wire resistance and so on).
Without a PDK for a technology we can not design the analog stuff inside 'cause we still miss all the concrete values for the layers to calculate transistor and wire sizes.
- alternative: internal hand-crafted RAM-cells
Designing internal RAM cells, no matter whether dynamic RAM or static RAM isn't possible without the analog values from the PDK..
- possible pathes to go
* Reducing the Operating System to smaller memory footprints (e.g. with NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU
* Getting a PDK and design with a couple of iterations in silicon our analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works..
'''' Note: if we'd start with an alien PDK we had to re-design the analog stuff from ground up again for our LibreSilicon PDK again.. ''''
If you have some suggestions how to get out of our chicken-and-egg-Problem, please drop us an email :-)
Regards, Hagen _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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DRAM DDR3 without leveling IS an option. We don't need special pads and can just use the I/O pads :-) https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/an... an520.pdf There we go! =^_^=~~~~~ On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote:
Meeting Minutes of the Mumble session today ===========================================
Participants: Devon, tatzelbrumm (partly), hsank, leviathan
Topics ------
- (external) RAM
While thinking about an RISC-V CPU demonstrator, we need memory for loading an Operating System like Linux.
Our first guess was for the demonstrator just to use external RAM chips, e.g. with HyperRAM, which has a quite simple interface and can be driven without LVDS-IO-Pads (which are still not available for us). Unfortunately using a couple of them gets fast quite expansive.
Using commercial available (and cheaper) DRAM nowadays is out of reach for us - this chips using a proprietary interface called DDR2 or DDR3. This interface needs differential IO-Pads (the LVDS we already mentioned above) and is critical about timing (in the meaning of different wire length, wire resistance and so on).
Without a PDK for a technology we can not design the analog stuff inside 'cause we still miss all the concrete values for the layers to calculate transistor and wire sizes.
- alternative: internal hand-crafted RAM-cells
Designing internal RAM cells, no matter whether dynamic RAM or static RAM isn't possible without the analog values from the PDK..
- possible pathes to go
* Reducing the Operating System to smaller memory footprints (e.g. with NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU
* Getting a PDK and design with a couple of iterations in silicon our analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works..
'''' Note: if we'd start with an alien PDK we had to re-design the analog stuff from ground up again for our LibreSilicon PDK again.. ''''
If you have some suggestions how to get out of our chicken-and-egg-Problem, please drop us an email :-)
Regards, Hagen _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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Hi, What about "outsourcing" the memory controller over HyperRam? If we can do HyperRam, we could have a controller that translates HyperRam to DDR2/DDR3? Our CPU <-> HyperRam <-> Controller <-> DDR2/3 <-> DRAM chips Just an idea... Best regards, Philipp Gühring
Hi The thing is that I wanna reduce the amount of proprietary IP on the PCB. I also considered the solution of making a simple converter, which basically contains only a DDR3/4 controller as well as a HyperRAM interface, but considering the overhead, it might actually be more practical to just try to use the DRAM over bit banging. It has been done already on FPGAs without specialized pads and it seems to be working, just without the maximum transfer rates. However, the solution over bitbanging probably is still the better solution IMHO, because it doesn't have the overhead of yet another component in between. Cheers -lev On Saturday, July 24, 2021 8:38:53 PM WEST Philipp Gühring wrote:
Hi,
What about "outsourcing" the memory controller over HyperRam? If we can do HyperRam, we could have a controller that translates HyperRam to DDR2/DDR3?
Our CPU <-> HyperRam <-> Controller <-> DDR2/3 <-> DRAM chips
Just an idea...
Best regards, Philipp Gühring _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
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participants (4)
-
David Lanzendörfer -
Hagen SANKOWSKI -
Ludwig Jaffe -
Philipp Gühring