Hello List!
Today I came across this nice RAM Generator:
https://github.com/VLSIDA/OpenRAM
Usually, all the Memories on the Die are generated. This means, a Vendor provides a Script to generate the memory-structure with address decoders, storage cells, output buffers, build-in tests etc.
Well, such a script I found on Github, and it is in Python. If it is working, or at least we could adapt it to provide sufficient memories, I am fine with that.
In a good Borg-manner, we should assimilate OpenRAM into QtFlow.
This scripts would helps a lot to design the first Microcontroller. Sometimes I really like github.com :-)
Regards, Hagen.
Hello Hagen,
Today I came across this nice RAM Generator:
https://github.com/VLSIDA/OpenRAM
Usually, all the Memories on the Die are generated. This means, a Vendor provides a Script to generate the memory-structure with address decoders, storage cells, output buffers, build-in tests etc.
I am familiar with this project and the two main groups involved with it, Matt Guthaus at U.C. Santa Cruz, and James Stine at Oklahoma State U. Integrating this into efabless and/or qflow is a very high priority for me. The main difficulty with integration is the need to design the analog components for each targeted process. There are no particular issues that I know of; it just takes a lot of time to do it.
If any of you wants to talk with Matt or James, I can make introductions.
Regards, Tim
+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Hello Tim!
On 05/29/2018 07:23 PM, Tim Edwards wrote:
I am familiar with this project and the two main groups involved with it, Matt Guthaus at U.C. Santa Cruz, and James Stine at Oklahoma State U.
Great!
Integrating this into efabless and/or qflow is a very high priority for me. The main difficulty with integration is the need to design the analog components for each targeted process. There are no particular issues that I know of; it just takes a lot of time to do it.
I'll like to do that - just after I finished the test structure wafer and later than the StdCellLib..
Tim, as I understood, this Generator could be adapt also to generate ROM structures as well? We just have to provide the analog primitives for that, right?
Regards, Hagen.
Hi Tim
I am familiar with this project and the two main groups involved with it, Matt Guthaus at U.C. Santa Cruz, and James Stine at Oklahoma State U. Integrating this into efabless and/or qflow is a very high priority for me. The main difficulty with integration is the need to design the analog components for each targeted process. There are no particular issues that I know of; it just takes a lot of time to do it.
I've been in contact with the folks as well and know the project. However, we don't have SRAM cells yet for the scripts.
If any of you wants to talk with Matt or James, I can make introductions.
Yeah. Please invite them to join coming Sunday 9pm HKT in our mumble conference in the channel "IC" on murmur.lanceville.hk!
Cheers David
libresilicon-developers@list.libresilicon.com
-
David Lanzendörfer -
Hagen SANKOWSKI -
Tim Edwards