A differential pair driver and receiver would be an extremely important strategic addition that would form the basis of LVDS, MIPI, PCIe and protocols based on it, SATA, USB2, USB3 and more.

That's a heck of a lot of protocols covered, an extremely high bang per buck ratio.

Variants can be to change the impedance eg for DDR3/4 however just dropping in some resistors inline would be a temporary substitute, so it is not so essential (impedance matching on DDR3/4 is absolutely essential and is done dynamically by the PHY)

Hi

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That's a heck of a lot of protocols covered, an extremely high bang per buck ratio.

Well, I already put differential driver and receiver on my personal wish list. Unfortunately my skills in such analog cells are kind of limited.. Someone with more knowledge and experience in this area should take the task. And, as long as we are in the higher voltage supply range differential IO cells are not so quite common. This cells become more interesting with 3.3 Volt and below.

Yes. We right now are not remotely in the frequency range, where such cells would make sense.

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Variants can be to change the impedance eg for DDR3/4 however just dropping in some resistors inline would be a temporary substitute, so it is not so essential (impedance matching on DDR3/4 is absolutely essential and is done dynamically by the PHY)

You mentioned MIPI in the list above also - this seems to be very challenging, the voltage drop between high and low is smaller than LVDS. But yes, MIPI is nowadays everywhere in cheap devices, from cameras to displays and entering the IoT market also.

So it would be nice if someone of you takes the task

Mohamed from eFabless offered us help, as soon as we've got the process datasheet done. eFabless has some pretty experienced analog designers. I suggest we work together with them, as soon as Victor and I have reproducible results which warrant a measurement for simulation models and the data sheet. We're not quiet there though.

-lev

Hi

130nm is the point at which DDR3 can reach 400mhz. that's actually viable.

We're working on one micron right now...

Yes! Of course! As soon as we've going submicron, DDR3 becomes a topic. Especially because we need DRAM for our SoCs and CPUs

Cheers David

On Tuesday, February 26, 2019, Ludwig Jaffe ludwig.jaffe@gmail.com wrote:

Hi David, what memory tech can we do? DDR?

Getting hold even of DDR3 RAM ICs is troublesome. LPDDR3 is ok (and pricing ok), DDR3x16 is ok (for now), DDR3x8 is *NOT* ok, I know of only one company that can do 4gbit ICs here in Taiwan and I had to buy 5000 @ USD 3.30 each for them to actually bother.

DDR2 would almost certainly be a total waste of time.

SDRAM doesn't do DDR, it is basically the ISA bus aka Flexbus aka IDE aka AT/XT aka PCMCIA aka CompactFlash aka MCU 8800 Bus aka NAND Flash bus they are hilariously all the same signalling.

Even implementing DDR3 is risky as it is going out of fashion since apple and intel products started dominating foundry supply with massive DDR4 orders, no spare capacity to make DDR3, which was why China opened up some DRAM foundries last year (and probably why the bunfight between US and China, accusations of theft etc blah blah zzzzz).

Seriously considered talking to fabless companies, combine OpenRAM with 4 to 8 HyperRAM interfaces. Would not need the mad timings and dynamic impedance matching. HyperRAM is diff pair on the clock line only when put into DDR mode. Only goes up to 150mhz clock rate so 300mbytes/sec in DDR mode. Bit like SDMMC. Also DDR mode only doable in 1.8v.

HyperRAM another one where diff pair Rx and Tx needed although Tx is just a NOT gate on one line. Rx bit more complex, need comparator to check which CLK line is hi which is lo.

L.