Wishbone will be a nice bus

On Sunday, July 8, 2018, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:

Hello List The result of this meeting has been:

• We have to get rid of the AMBA (AXI) bus, because it's proprietary and

ARM will make our life a living hell as soon as we start taping chips out using it and sell these chips. So I'm now digging deep into the base system of Rocket-Core and modify it, so that it starts using Wishbone instead.

• We've got signed the contract now, so I should get my access RFID-card

to the clean room this week or so.

Cheers -lev

On Saturday, 7 July 2018 6:29:37 PM HKT Hagen SANKOWSKI wrote:

...

Hello List!

Just a small reminder for our next Mumble Sessions on this Sunday, July 8 at 21.00 Hong Kong Time.

Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC.

On the agenda are (at least) this topics

• current status
• test wafer status
• other stuff around libre silicon

Happy to hear from you! Hagen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel

Hi The question isn't whether it's royalty free or not. The question is rather, whether ARM can sue us for breaking the law by using the AXI4 bus inside our ASICs, which we might also sell to customers the US government doesn't like. Or plain: Is it free or is it unfree? Can we use it without patent issues? Does ARM still require us to get a license from them in order to use it? If yes we might be in quiet a bit of a trouble here, because we can't guarantee to fulfill the standard clauses in US export agreements. We need someone to check before we start developing and selling products based on this interface. Not that I worry too much about possible sanctions from the US because we still have access to the whole Chinese market. And no one at the border will be able to check, whether these manufacturers from Shenzhen have soldered our chips onto their PCBs or not. But ironically my partners from China worry about avoiding legal issues with the united states.

Cheers David

On Monday, 9 July 2018 10:21:07 PM HKT Staf Verhaegen wrote:

Although I do think Wishbone should be preferred bus I would like to know if you any reference backing up your statement about AMBA bus ? On wiki page it is said that it is open-standard and can be used royalty free.

Also did you check Tile-Link/Chip-Link?

On Jul 9, 2018, at 8:10 PM, Mohammad Amin Nili manili.devteam@gmail.com wrote:

Hello David,

Would you mind make a brief comparison between AXI4/AMBA and Wishbone? I’m wondering to know about the most important achievements if we use AMBA rather than Wishbone.

Best regards, Manili

...

On Jul 9, 2018, at 8:03 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:

Hi The question isn't whether it's royalty free or not. The question is rather, whether ARM can sue us for breaking the law by using the AXI4 bus inside our ASICs, which we might also sell to customers the US government doesn't like. Or plain: Is it free or is it unfree? Can we use it without patent issues? Does ARM still require us to get a license from them in order to use it? If yes we might be in quiet a bit of a trouble here, because we can't guarantee to fulfill the standard clauses in US export agreements. We need someone to check before we start developing and selling products based on this interface. Not that I worry too much about possible sanctions from the US because we still have access to the whole Chinese market. And no one at the border will be able to check, whether these manufacturers from Shenzhen have soldered our chips onto their PCBs or not. But ironically my partners from China worry about avoiding legal issues with the united states.

Cheers David

On Monday, 9 July 2018 10:21:07 PM HKT Staf Verhaegen wrote:

...

Although I do think Wishbone should be preferred bus I would like to know if you any reference backing up your statement about AMBA bus ? On wiki page it is said that it is open-standard and can be used royalty free.

---

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On Mon, Jul 9, 2018 at 6:07 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:

•   Tile-Link/Chip-Link[3] [4] doesn't seem to have been patented yet and seems
    to come from universities and the like.
  

tilelink has the disadvantage that it was designed by people who think in high-level languages. i don't believe they ever actually looked really closely at the auto-generated verilog and thought, "if this standard became popular and people tried to implement it from scratch in verilog or VHDL, how much effort would they need to expend?"

consequently it's hell to implement in anything other than an OO-based HDL. IIT Madras, who are using Bluespec, are having well-above-average difficulties implementing it.

[1] https://patents.google.com/patent/US7069376B2 [2] https://patents.google.com/patent/US20050138253

fun as it would be to get into a pissing contest with ARM and have all the claims invalidated by crowd-sourced prior art searches like cloudfare did against that patent troll last year, we have better things to do with our time.

l.

Hello.

On 07/10/2018 06:38 PM, Mohammad Amin Nili wrote:

I tried to search google to find some proper and accurate comparison of AMBA (specially AXI4) and Wishbone (or even other bus protocols) from every aspects (e.g. license, specs, features, throughput etc.). All papers are very old (outdated) or not very useful. Anybody could help me?

Well, we have to compile this comparison. Let's start this way - collecting first the aspect we like to compare and than getting the informations. I can help somehow while having experiences with a couple of such System-on-Chip busses; but I do have limited resource collecting all details.

So, AMBA is a bundle of different busses.

Mostly known is APB (AMBA Peripherial Bus) for relaxed bandwidth (two cycles for one data transfer IMHO). Defined someone in the 90ies.

Next, on same Age is AHB (AMBA High Performance Bus) for better bandwidth (one clock cycle per data transfer) defined for the first available ARM cores.

AMBA AHB is comparable with Wishbon, IMHO. Both do have a handshake mechanism, so every data transfer has to be acknowledged from the receiver cycle by cycle.

Most attention in the current days the AMBA AXI bus gets while promoted by ARM and Xilinx (as an FPGA vendor). This AXI does not have the handshake mechanism anymore, so data can be blown out without waiting the acknowledge from slave, and can be cached sometimes on longer bus lines without timeouts. For that, the bus is splitted into three sub-busses, one for writing, one for reading, and one for control.

For Specs, you have to be registered account on ARM. https://developer.arm.com/products/architecture/amba-protocol

Regards, Hagen.

Hi

...

fun as it would be to get into a pissing contest with ARM and have all the claims invalidated by crowd-sourced prior art searches like cloudfare did against that patent troll last year, we have better things to do with our time.

For a SoC without any ARM IP I agree with David it's best to stay away from using AMBA bus. Even if a law suit would/could be won it's a real PITA.

Ok. Then we're on the same page here. Because PicoRV32 is using the axi bus as well, we can't use this core for our MCU/SoC either. We will have to bootstrap our own SoC/MCU using Chisel3 and rocket-chip as a basis, essentially stripping the rocket-chip of all AXI-stuff and re-adding the features, but hooked up directly over TileLink instead. I guess the only reason eFabless with their Raven didn't get into trouble yet is because there were just some managers at ARM hysterically laughing when they've read the tape out volume and orders of this MCU. But as soon as we start providing a free technology node and open layout and sell the part as off-the-shelf part they might become pretty nasty and try to hurt us any way they can, including law-suits (even though futile, as we've all determined)

Cheers David

Hi Tim The advantage about rocket-chip is: It already provides an interface called TileLink which is free of potentially nasty legal surprises and it can be easily customized using Chisel3. Also there are already IP cores in Chisel3 (like UART and SPI) available which can be easily hooked up to the TileLink interface. It's pretty straight forward actually. I'll be gladly using Cliffords yosys for synthesizing the output into a netlist afterwards though :-)

Cheers David

On Thursday, 12 July 2018 10:26:48 PM HKT R. Timothy Edwards wrote:

Have you considered just asking Clifford for a wishbone implementation in the PicoRV32 code?

Compared to the amount of work to write and debug the PicoRV32 core, the AXI bus adapter is a trivial add-on. The PicoRV32 is open-source and Clifford is a fantastic open-source developer. I expect he would be able to toss a wishbone bus adapter into the PicoRV32 code faster than you could get anyone else to do it, or do it yourselves.

Hi Oha. Didn't wanna put the PicoRV32 a bad light or so. And thanks for the info! Didn't know that PicoRV32 had a native wishbone interface. Neato! Clifford told me a while ago that the chips wouldn't be supposed to be taped out, and that he specifically made it for FPGA use only. He was actually kindof annoyed that everyone seems to ignore his warnings about the core not being suitable for silicon implementation. So I figured it's maybe anyway a better idea to look out for alternatives.

What I really liked about rocket-chip is the nice abstraction of auto code generation and modularity.

I mean, I can change it for instance from a 32 bit to a 64 bit architecture with a few simple lines of code and the periphery stays connected.

And I was thinking it would be a good exercise to try producing a simple MCU with rocket-chip and afterwards upgrading it to a full multicore SoC with DRAM port in a further tape out.

That's just how I see it and I'm happy to be taught differently :-)

Cheers David

On Friday, 13 July 2018 12:05:03 AM HKT Tim Edwards wrote:

You seem set on the rocket-chip, which is of course your decision to make.

However, just to set the record straight:

(1) The AXI-lite bus adapter is used in a simple wrapper around the picorv32, which itself does not define a bus protocol. To make use of it, you would just synthesize "picorv32_axi" instead of "picorv32".

(2) There is an additional wrapper in the picorv32 source for wishbone, for which you would simply synthesize "picorv32_wb" instead of "picorv32". It's all already there (Clifford had to remind me of this because I had forgotten that there was a wishbone-compatible wrapper in the verilog source).

So just to be sure that you are not misrepresenting Clifford's work, the statement "Because PicoRV32 is using the axi bus as well, we can't use this core for our MCU/SoC either" is simply false.

--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Jul 9, 2018 at 4:52 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:

Hi

...

Would you mind make a brief comparison between AXI4/AMBA and Wishbone? I’m wondering to know about the most important achievements if we use AMBA rather than Wishbone.

Depending whether we need to apply for a license for using AXI4/AMBA, this might be a problem especially for you, since you're in Iran.

https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture

i checked with the UK trademark database: there are 8 trademarks for the exact word "AXI" - none of them with ARM - and 23 for the exact word "AMBA". i checked the first few (1996, 1997), which would have been the priority filing date for AMBA (first created in 1996) and neither of them were by ARM.

the ever-reliable 100% factually correct wikipedia states happily that it's "100% open!!!!"

l.