Hi Ferenc, Hi everyone

Looks great! Finally, we can fine-tune the electrical parameters.

Yeah. About that. The threshold is still totally off and the RDon is at around 1kOhm ^^' The reason: The ndoping in the pchannel is still way to high, because I haven't performed the pbase and nbase implant steps, which will add around another 2 hours of thermal budget, which should dilute the dopants to the desired channel carrier concentration.

But see it positive: Then we automatically get LDMOS and BJT as well :-)

However, I have some questions:

• What is plot against what? The vertical axes are not visible on the

image...

It's micro amps... As I've mentioned, the charge carrier values are still totally off on this sample, until I've made the pbase and nbase ^^' But as soon as I've got pbase and nbase, the thermal budget will adjust automatically. At the moment it's behaving as expected from my modeling: A barely conducting transistor, but switching.

• What is the black spot on the contact areas?

That's another reason, why the gain is absolutely crap at the moment. That's not properly etched oxide.

The smaller the holes, the longer the dry etching needs to get through the LTO on top of the contacts.

Also, I've got another problem: 5 minutes RTP annealing isn't cutting it. Some of the Source-Drain channels in the PMOS samples are shorted and give me the resistance of highly doped nsubstrate according to the calculations from my thermal budget. This means, that the junctions were not enough deep in some areas and were fully consumed by the silicide formation. This means I've got to put the wafer into the furnace after nimplant+pimplant and anneal it for 40 minutes at 900 degrees C.