November 2018 - Libresilicon-developers

Xic
by Tobias Kaiser 16 Nov '18

16 Nov '18

Hello, great to hear from the list that you guys are making some progress! I recently stumbled upon the open-source IC design software Xic [1], which includes schematic entry, layout and simulation. It is quite easy to install and I liked it quite a bit. I thought this might be interesting for LibreSilicon at the current stage, as an alternative to Magic or QtFlow. Best wishes Tobias [1] https://github.com/wrcad/xictools

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Metalcaps and beta release
by David Lanzendörfer 15 Nov '18

15 Nov '18

Hi Ferenc We decided that it's too risky to include the caps for the alpha release, especially because we're now under pressure to deliver at least something for the congress. So Hagen and I decided that we just go ahead now and at least get the alpha release working. It's pretty cheap to make mask sets at the university where we're prototyping, so we will manufacture another mask set after the congress which will include caps. Priority right now is to get CMOS working. I hope that's ok. Cheers David

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Chaos Communication Congress assembly
by David Lanzendörfer 14 Nov '18

14 Nov '18

Hi all Everyone who would like to join the 35c3 in Leipzig has now the last chance to order one online. Afterwards without insurance of availability there might be some left to buy on arrival, but I wouldn't suggest gambling: https://tickets.events.ccc.de/35c3 We've got the big talk accepted, so be prepared for a 1.5 hour talk from Hagen and me at the congress. Hope to see you there. Also please tell me if you come to the congress so that we can allocate a space for you to sit in our assembly. Cheers David

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Metal caps
by David Lanzendörfer 12 Nov '18

12 Nov '18

Hi Ferec I've been thinking about reducing the energy of the nimplant/pimplant field implant steps and then making the implant stop nitride layer thinner on top of the diode so that we can use that nitride layer as as well as dioelectricum. So we could have polysilicon, then nitride, and then a metal layer on top. Would do you say? Nitride is a high-k material with a relative permittivity of around 7-8 compared to silicon oxide with around 4. I think a junction with 50nm depth still is good enough? Cheers David

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Process concerns
by Éger Ferenc 07 Nov '18

07 Nov '18

Hello David, Acc. to the last conversation, the following concerns are identified (some may be RTFM): - Step 8.3 equipment is incorrect - Also step 8.3, is a tunnel oxide of 40nm thick is thin enough, or we need thinner? - Between 13.8 and 13.9, a cleaning step seems to be missing - When are the drain/source implants driven in? Is the annealing during silicide formation sufficient for drive-in? - The implantation dose and acceleration for the wells and the base/emitter layers are the same. - Implant stop nitride is 40nm grown, but etching is only for 10nm. - Al etch time is for 600nm, but the metal layer is 620nm thick. Also, will the Al etcher pass trough Ti? Regards, Ferenc

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Re: [Libre-silicon-devel] PearlRiver contact_meas
by Éger Ferenc 06 Nov '18

06 Nov '18

Hello Hagen, You are right, this is a four-terminal (a.k.a. Kelvin-contact) approach with one pair of conductors for voltage sense and another for current forcing. The metal1-ndiff is a bit different from the others, but this is a compromise: I had to squeeze it between the two pads, and I did not want the perpendicular diff. track to be meandered back under the pad. The reason for the well contact is to ensure that the well is biased to a known potential. Normally, it would be a fifth pad used as a kind of "shield", but since the equipment has only four probes, I chose to tie it to one of the current force leads. The reason for not having a separate pdiff (or other front-end layer) contact is that in the process all contacts will have a silicide layer over the diffusion, and that will cause the semiconductor to be degenerated (neither p, nor n-doped, with the interface between the silicide and the underlying doped layer is either ohmic or degenerate schottky barrier), so contact resistance will be mainly determined by the silicide layer, that is assumed to be the same for all front-end layers. (the behavior of the silicide-doped layer interface is handled in the MOSFET characterization.) Regards, Ferenc On Tue, Nov 6, 2018 at 5:46 AM Hagen SANKOWSKI <hsank(a)posteo.de> wrote: > Hello Ferenc. > > I like to re-add your measurement structures for contacts again into the > Pearlriver_quarter structure.. unfortunately I have to re-arrange the > test pads.. > > Well, looking at your structures I am wondering, what your design > intentions are. > I assume you´re like to do "Kelvin-Structures", e.g. described at [0]. > This are implemented 'clean' for via and via2. In case of poly and ndiff > i did not fully get the points. > > Can you explain me (or the list) in more detail? E.g. > - Why you connect the pwell also/only on one side? > - Why this are not completely symmetric on all axis? > - Why there is no pdiff contact structure also? > > Just for curiosity also, I always like to learn :-) > > > Regards, > Hagen. > > [0] https://ris.utwente.nl/ws/files/5463631/stavitski.pdf >

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Re: [Libre-silicon-devel] Paper search
by paulwuertz＠posteo.de 06 Nov '18

06 Nov '18

Sci-hub.tw is our friend! Really works like a charm, if you search for something else :) P.S. sorry for disappearing for quite a while from all activities, but I will try to push something in the next week again (finishing the lefdef and alf lib is still a thing :?), just read through all the mail I missed. I started working a while ago and university takes some more time for one missed exam, but I still plan on writing my diploma thesis next year about the libresilicon tool chain ^^El 6 nov. 2018 6:37 AM, Hagen SANKOWSKI <hsank(a)posteo.de> escribió: > > Hello Everybody! > > I am wondering whether someone of you has access to the following paper: > > "A simple approach to understanding measurement errors in the > cross-bridge Kelvin resistor and a new pattern for measurements of > specific contact resistivity" > (Mizuki Ono, Akira Nishiyama, Akira Toriumi : Solid-State Electronics 46 > (2002) 1325-1331) > > > and give me some help. > > Regards, > Hagen. > _______________________________________________ > Libre-silicon-devel mailing list > Libre-silicon-devel(a)list.o2s.ch > http://list.o2s.ch/mailman/listinfo/libre-silicon-devel

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Paper search
by Hagen SANKOWSKI 06 Nov '18

06 Nov '18

Hello Everybody! I am wondering whether someone of you has access to the following paper: "A simple approach to understanding measurement errors in the cross-bridge Kelvin resistor and a new pattern for measurements of specific contact resistivity" (Mizuki Ono, Akira Nishiyama, Akira Toriumi : Solid-State Electronics 46 (2002) 1325-1331) and give me some help. Regards, Hagen.

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New Pearlriver toplevel available
by Hagen SANKOWSKI 05 Nov '18

05 Nov '18

Hello Everybody! According our mumble session yesterday I now rectified the 'PearlRiver_die'. [0] Changes are: - size is now 4.3 x 4.3 mm^2 - long 2000 R-Square lines for NWELL, PWELL, NBASE and PBASE are added around the edges - all tables inside pearlriver_quarter are cramed Yesterday we also talked about the mosfet-alignement structure, which is still in the repository, but was recently gone off die. With changes today we have sufficient space for adding again. Still missing from my point of view are the diodes - substrate -> nwell, - pbase -> nwell, - pdiff -> nwell. This is work-in-progress. Please look at the structures and find the issues and send your comments and changes regarding the PearlRiver Testwafer ASAP at least to the list or via pull-requests on github. We are close before review - we like to order the masks a week later! Best Regards, Hagen [0] https://github.com/chipforge/PearlRiver

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Mask inversion
by Éger Ferenc 05 Nov '18

05 Nov '18

Hello Everyone, Here is my evaluation of necessary mask inversions: - nwell: darkfield - pwell: darkfield - pbase: darkfield - nbase: darkfield - sti: brightfield - fox: darkfield - sonos: brightfield - gate: brightfield - implant block nitride: brightfield - nimplant: darkfield - pimplant: darkfield - silicide block: brightfield - contact: darkfield - metal{1|2|3}: brightfield - via{1|2}: darkfield - glass: darkfield Regards, Ferenc

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Libresilicon-developers November 2018