March 2018 - Libresilicon-developers

Question: STI *after* wells? Alignment.
by David Lanzendörfer 29 Mar '18

29 Mar '18

Hi What do you think about building the box isolation after constructing the wells? Any apparent downside on this I'm overlooking? Cheers David

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Keep in Mind - today mumble session at 3:00 pm (Central Europe "Summer" Time)
by Hagen SANKOWSKI 25 Mar '18

25 Mar '18

Hello List. Keep in mind that our Mumble Session is always at Sunday 9:00 pm Hong Kong time - this means today at 3:00 pm Central Europe Summer Time. See you, Hagen.

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Question: CMP vs. BHF
by David Lanzendörfer 24 Mar '18

24 Mar '18

Hi During the meeting we found out that we don't need a nitride hard mask but can use an oxide mask in order to etch silicon with a plasma etcher. Also I've found out that the variation of the CMP machine is terrible (~5um!) Now that we have oxide should we just skip the CMP step and just grow our process oxide for the n-well/p-well construction over it? @Staf: Can you maybe join this weeks mumble meeting and give some feedback? I'll update the document until then, so that we can discuss it. Cheers David

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Donations for LibreSilicon
by David Lanzendörfer 23 Mar '18

23 Mar '18

Hi I've been approached now more than once already on Twitter about the possibility to donate to our project. However: We're not having any legal form for the open source project yet and the company can't receive donations because this would be a problem from the legal perspective and taxes and so on. Also it's a problem if I register a society receiving donations and being the CEO of the company doing the commercial part of selling semiconductor products as soon as we've got the open source process working and we can actually also mass manufacture with it... @Hagen: Do you wanna talk with Tobias about registering a society (Verein) in Berlin for LibreSilicon where the Wau Holland Stiftung could collect donations for and transfer to that society? Then this society could basically pay Lanceville to develop the open source process and could also buy development boards which we could give out for free to Hackers at the congress. However, since you will be holding shares in the company as well we should maybe appoint someone else (for instance Tobias) as the founder of the society, so that no legislator develops the idea that we would have criminal intends. Especially because of the fact that we're working on developing a free process and technology node might at some point be reason enough for some lawyers of big proprietary and evil foundries to try eliminate this unpleasant backdoor free competition, and such a legal thing might be the welcome cross-hair they're looking for. So we have to make sure that there is nothing with this where someone could construct a legal case with and hang us with it. Cheers David

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Testing equipment: Pads
by David Lanzendörfer 22 Mar '18

22 Mar '18

Hi The probe is placed manually. The diameter of the pin is 20 micro meters. @Hagen: That means our pads should be at least 40x40 micrometer I guess. And don't forget that our minmum line spacing is 500nm! Better make 1um spacing! Cheers David

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Wafertest structures - Overlay
by Hagen SANKOWSKI 21 Mar '18

21 Mar '18

Hello. I just grep my folder with essential notes I collected over the years and stumbled across the Overlay problem [1] and [2]. Do we need dedicated structures on the Test-Wafer for that? Just for curiosity how good the machines are and our handling is?? Regards, Hagen [1] https://de.wikipedia.org/wiki/Overlay_(Halbleitertechnik) [2] https://en.wikipedia.org/wiki/Overlay_control Btw, the German Wikipedia Article is better than the English one in this case.

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IEEE document required
by David Lanzendörfer 20 Mar '18

20 Mar '18

Hi We need the following IEEE document: IEEE Transactions on Semiconductor Manufacturing ( Volume: 12, Issue: 3, Aug 1999 ) Date of Publication: Aug 1999 (Page(s): 288 - 294) Who of you folks can get their hands on a PDF or so? Cheers David

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JSON vs. TOML
by David Lanzendörfer 20 Mar '18

20 Mar '18

Hi I've now been fighting for two days with TOML and its C++ library and I've come to the conclusion that JSON would be the better format for us for many reasons, which would be for instance: * Easier to express hierarchical lists. * More reliable library support @Hagen: I'm tempted to port your TOML file over to JSON, if that's ok with you. Cheers David

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Process Layer Definitions as TOML file
by Hagen SANKOWSKI 19 Mar '18

19 Mar '18

Hello List! I already talked about, that I do like to have a technology definition file, just for reading into the (Magic) Layout editor and get ready to work with. TOML (https://github.com/toml-lang/toml) is doing the job quite well. So I wrote now the very first process definition file I like to share with you. Please check the attachment of this email. As you can see there are definitions for every layer we are currently using - please check this twice, so we do not miss anything. Annotated to every layer are the GDS II (https://en.wikipedia.org/wiki/GDSII) layer numbers and the CIF (https://en.wikipedia.org/wiki/Caltech_Intermediate_Form) layer names. My informations came from the MOSIS SCMOS-Design Rules document (https://www.mosis.com/files/scmos/scmos.pdf) we like to use for our technology also. And, well, I hope I get fancy colors for every layer. If you like to look at such color definitions, I would recommend you the latexlolor.com website. Later we should feed the ls1u.toml file with specific technology values like resistance and so on - might be also with the design rules numbers (as seen in the SCMOS document from MOSIS above), e.g. Rule 15.1 with 6 lambda. Regards, Hagen. -- "They who can give up essential liberty to obtain a little temporary safety, deserve neither liberty nor safety." Benjamin Franklin (1775)

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Mumble session
by David Lanzendörfer 16 Mar '18

16 Mar '18

Hi Who's around this Sunday for the mumble conference around 9pm HKT? We have to start developing our test wafer layout. Cheers David

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Libresilicon-developers March 2018