April 2018 - Libresilicon-developers

Standardized Data Structures Lef/Def routines
by p4w5 12 May '18

12 May '18

Hej everybody! Sorry for not joining mumble sessions, I feel a little of on communications, but anyway, hope my question finds some positive echo ;) As I tried to understand project structures of the whole design flow - correct me if I am wrong - each part of the program uses its own file formats or parsers as data structures for macros and layers, from what I skimmed: * Graywolf uses a YACC parser for some file formats (don't know which) * in the qflow repo is some form of lefdef parser using YACC, where I am not sure if it is just for some UI stuff or supposed to be a actual parser * in qroute 20% of the LOCs are for lefdef parsing with a hand written parser I am not sure if there are some more forms of lefdef readers? So my general plan would be to write a more generic router (being more algorithmic agnostic providing a general data structure, to experiment with some routing algorithms, splitting in global and detailed routing and so on). Before dealing with this I would opt to have some common core dealing with lefdef reading and writing. Is there maybe already some tool doing this? In the last week I started going through the lefdef ref manual 5.8 and to manually parse lef files into some c++ structs, see[1] to have a look yourself. From quite some big lef files it already can parse >90% the mayor chunck. Being quite uncommented and not tougth through to much, but before wasting more time on this I wanted to get some feedback. Is the general lefdef-lib thing a idea worth spending more energy on? Is there already another attempt to do so in progress? Thanks for information and feedback! P.S. Is there already something up for the hackathon? Would be definitely up for it ;) Paul [1] https://github.com/paulwuertz/siliconverter

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Tool Chain Hackathon
by Hagen SANKOWSKI 01 May '18

01 May '18

Hello List! As you might notice I am organizing currently a Libre Silicon Hackathon. We like to polish up the Tool Chain, which David already forked on github. [0] Well, this seems to be something more software-based, for everybody which is not so familiar with the ASIC design flow. I like to put this items on the agenda for the Hackathon - introduction into the ASIC design flow - checking the code base of FOSS tools which are already there - brainstorming new approaches for more modern tooling - hacking, eat, sleep, repeat While looking for a nice space, it is difficult to find a date in May. There are some holidays and some bigger events like the Gulaschprogrammiernacht. [1] Well, I got already one feedback from Dresden over Whitsuntide / Pentecost and set up a doodle poll request for that location. [2] Other locations should/might follow. BTW, I like to provide a cool Hackathon T-Shirt for every participant also :-) Regards, Hagen Sankowski [0] https://github.com/leviathanch/qtflow [1] https://entropia.de/GPN18 [2] https://doodle.com/poll/hv3ezxtak769g9d5

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Re: [Libre-silicon-devel] Standardized Data Structures Lef/Def routines
by Hagen SANKOWSKI 28 Apr '18

28 Apr '18

Hello Paul. My notes below. On 04/28/2018 06:01 AM, p4w5 wrote: > Before dealing with this I would opt to have some common core dealing > with lefdef reading and writing. Is there maybe already some tool doing > this? > In the last week I started going through the lefdef ref manual 5.8 and > to manually parse lef files into some c++ structs, see[1] to have a look > yourself. From quite some big lef files it already can parse >90% the > mayor chunck. Being quite uncommented and not tougth through to much, > but before wasting more time on this I wanted to get some feedback. > > Is the general lefdef-lib thing a idea worth spending more energy on? Is > there already another attempt to do so in progress? Yes, you are right, the tools mostly dealing with LEF/DEF formats somehow. But for me, LEF/DEF is nothing more than an export format. Let's look at the dataflow for the ASIC design to describe why I think so. First, someone is writing the RTL [0] code, mostly in Verilog [1], VHDL [2] or any other Hardware Description Language which is useful for that. Than a Synthesizer tool [3] translates this behavioral description into a so called netlist [4]. While the netlist is nothing more than a list of dedicated primitives like gates, Latches and other cells, this Synthesis tool already needs a bunch of information (even the timing/delays) about the primitives which are should used later in the layout. Yosys [5] as an FOSS synthesis tools uses the so called BLIF format [6] for that. Additionaly, someone want to add the stuff for testability here. Now, the netlist represents somehow the RTL design with primitives from the Standard Cell Library (BTW, I am developing the Standard Cell Library here [7]). Second, the designer now starts the layout by assigning the values for size of the die, doing all the floor planning stuff. [8] Here the physical sizes / layer of the primitives / Standard Cells are very useful to calculate the space, that is the point where LEF [9] and DEF [10] cames in. Both formates are just layer informations - they are not suitable for the synthesis step before. Third, the Place and Routing step needs the exact timing of the primitives / cells again while re-iterating many times through the netlist and find the best placement and routing regarding the constraints which already was used for the synthesis. And this step should use already technology information based on Resistance and Capacitance (every line is a RC-circuit [11] which produces a delay), called wireload model. Long distances producing longer delays, to short lines are also avoidable regarding the Setup- and Hold-Violations [12] Forth, while the design matches all constraints (in the meaning of operations frequency for every part) etc, now the layout of the die, the placement of the IO-Cells, the clock tree, the placed cells and all the wires are now transformed to the GDSII file [13] which goes to the foundry. So, from LEF / DEF to GDSII is the last step. IMHO, we should look at the ALF file format also [14] for the library. There are all informations we are needing for all steps, from synthesis to place'n'route and GDSII generation in one file format. This pure ASCII file format became a IEEE 1603 and IEC 62265 standard. But this format is dedicated for library elements (the Standard Cell Lib) - I am not sure we can use / re-use / expand it to our internal file format of the layout tool chain. I guess, we should use it for the layout also, keeping all the information together in one file format which could make a difference for our FOSS tools. All the tools for ASIC layout are quite old and limited; using cell delays (aka timing) or physical parameters of the process for better results are difficult with that old tools. While using ALF even for the layout, we are able to press the button and generate export formats (for user tools). On my list there are already as mentioned - BLIF - LEF / DEF and not mentioned - SDF. [15] I am currently organizing the hackathon for the tool chain - I'll send out today more about that. Let's make it better, let's make a difference! Regards, Hagen Sankowski [0] https://en.wikipedia.org/wiki/Register-transfer_level [1] https://en.wikipedia.org/wiki/Verilog [2] https://en.wikipedia.org/wiki/VHDL [3] https://en.wikipedia.org/wiki/Logic_synthesis [4] https://en.wikipedia.org/wiki/Netlist [5] http://www.clifford.at/yosys/ [6] http://bear.ces.cwru.edu/eecs_cad/sis_blif.pdf [7] https://github.com/chipforge/stdcelllib [8] https://en.wikipedia.org/wiki/Floorplan_(microelectronics) [9] https://en.wikipedia.org/wiki/Library_Exchange_Format [10] https://en.wikipedia.org/wiki/Design_Exchange_Format [11] https://en.wikipedia.org/wiki/RC_circuit [12] https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Timing_parameters [13] https://en.wikipedia.org/wiki/GDSII [14] https://en.wikipedia.org/wiki/Advanced_Library_Format [15] https://en.wikipedia.org/wiki/Standard_Delay_Format

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Reminder - next Mumble Session on April 29, 2018, 21.00 HKT
by Hagen SANKOWSKI 28 Apr '18

28 Apr '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, April 29 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - the a hackathon for the tool chain - other stuff around libre silicon Happy to hear from you! Hagen

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Other free silicon projects
by David Lanzendörfer 24 Apr '18

24 Apr '18

Hi List This fellow just made an amplifier work in his own lab: https://twitter.com/szeloof/status/988589833974140929 I've already PMed him but he seems reluctant to join the LibreSilicon project. Is someone near where he's living and can poke him physically until he joins our project? Thanks ^-^ Cheers David

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Reminder - next Mumble Session on April 22, 2018, 21.00 HKT
by Hagen SANKOWSKI 23 Apr '18

23 Apr '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, April 22 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - the test wafer structures - the tool chain, and a hackathon for the tool chain - other stuff around libre silicon Happy to hear from you! Hagen

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Mumble conference: ICO white paper
by David Lanzendörfer 09 Apr '18

09 Apr '18

Hi Here is the ICO white paper we've discussed in the Mumble conference. Glad for feedback: https://docs.google.com/document/d/1XdLKafFeYxJJ69Lj8CvbAB36MNBcKUnrF3OQehW… Cheers David

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Mumble Pad
by Hagen SANKOWSKI 09 Apr '18

09 Apr '18

Hello. Saved someone the yesterday mumble meeting notes on pirate pad? Today, as I want to look at that, the link is empty. Regards, Hagen.

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Literature List
by Hagen SANKOWSKI 08 Apr '18

08 Apr '18

Hello List. As today mentioned in our weekly mumble session - I am collecting useful literature for teaching "how to make chips" to others and attract even more people to our project. Well, afterwards I updated the lists, you'll find here at my StandardCell Wiki. And yes, I added the ISBN numbers now. The basics are on the Textbook page https://vcs.in-berlin.de/chipforge_stdcelllib/wiki?name=Textbooks with further links to more Books, in Englisch https://vcs.in-berlin.de/chipforge_stdcelllib/wiki?name=Literature_EN and German https://vcs.in-berlin.de/chipforge_stdcelllib/wiki?name=Literatur_DE Enjoy! Hagen.

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Feedback from last Talk at Würzburg
by Hagen SANKOWSKI 07 Apr '18

07 Apr '18

Hello List! Last Weekend, which was also Easter, I give a 30 minutes Talk about Libre Silicon in German. The event was organised from one local CCC chapter. You can find the Video of the talk here: https://media.ccc.de/v/WB99HE Well, now after a busy week, I like to share some feedback on our list. In the auditorium sitting around 25 people and the video above was already seen round about 100 times. - Oh, someone put this video on youtube also, where it has already more than 400 views. Awesome! - I think this is a good outcome. Afterwards I had a smalltalk with some guys on the floor in Würzburg, and also conversations by email. All I invite to our Email list and to take part active. One guy (Christian) came across with an Invitation from the lowRISC circle to write an article on LWN.net Let's take the momentum and a warm welcome to our new list members. I hope, we all meet us on Sunday, 21:00 HKT at mumble 109.109.202.102, Port 64738 in the IC channel. Regards, Hagen.

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