May 2018 - Libresilicon-developers

Process flow generator
by David Lanzendörfer 30 May '18

30 May '18

Hi I'm right now working on a process flow generator which generates LaTeX and from there a PDF out of a YAML file in which the process is nicely written down. The key is here that you can add requirements for preparation steps between machines and it automatically checks for contamination control violations. What do you think? Might that be useful for anyone else except us? For us it will be very useful, because we won't make mistakes when planning processes anymore, at least on the contamination level. Cheers David

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RAM for LibreSilicon
by Hagen SANKOWSKI 30 May '18

30 May '18

Hello List! Today I came across this nice RAM Generator: https://github.com/VLSIDA/OpenRAM Usually, all the Memories on the Die are generated. This means, a Vendor provides a Script to generate the memory-structure with address decoders, storage cells, output buffers, build-in tests etc. Well, such a script I found on Github, and it is in Python. If it is working, or at least we could adapt it to provide sufficient memories, I am fine with that. In a good Borg-manner, we should assimilate OpenRAM into QtFlow. This scripts would helps a lot to design the first Microcontroller. Sometimes I really like github.com :-) Regards, Hagen.

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Re: [Libre-silicon-devel] STA and Simulation in a workflow
by Hagen SANKOWSKI 29 May '18

29 May '18

Hello Andreas. On 05/29/2018 04:34 PM, Andreas Westerwick wrote: > Hello List, > > this question comes in two parts and is for hardware designers: > > In the Alliance CAD System there is a tool called `asimut`, which does > VHDL simulation and is executed after each step in the workflow > basically. I do not see the reason for doing the simulation *after* *each* step in the workflow. Before getting the netlist, you do intensiv simulations for verifying your design. Afterwards, with place and route already done, the STA checks, that your design still meets the timing requirements. As Tim mentioned, you probably could verify that your design is still sane after place and route - with self-checking testbenches. Seriously, only a minority of designers can write good / sophisticated testbenches. So my guess here is, that the tool flow in Alliance misses something like a equivalence checking tool - before and after one processing step. That would be fine to have a EQ check. I am not sure, but I think I heard something in that direction from Clifford, that Yosys could do that. Let put us the Equivalence Check on the check-list for QtFlow. Because if their are processing steps, which could be risky, or you would still not trust the fresh developed tools - a EQ check can recognize whether the design is still logcial/functional the same as it was before the processing step. > Is there an equivalent simulation tool in `qflow` or is it comparable > to `ng-spice`? > Would you execute `ng-spice` after each step in a hardware design flow? Definitely not. And just for the record - analog simulations in spice (or ng-spice) are very time and memory consuming. Yoo wouldn't do them without a good reason. If we starting with digital design, pure digital simulations in Verilog e.g. with Icarus Verilog, are quite faster. Analog simulations I would start, if I like so-called Mixed-Signal-Simulation with analog-parts (e.g. a ADC, DAC, or PLL is involved) and digital control logic coupled to them. > The second question is about finding an equivalent STA tool to `vesta`. > STA is performed after Placing and then again after Routing, is this correct? STA tools are checking, whether the design - from a perspective of timing - still reaches the timing requirements. While with placement there is not a trustworthy source of timing information, the STA becomes useful after the Routing step. With routing, the wires gets there delay. > I cannot find a similar tool in the Alliance CAD System but it is necessary > for a complete silicon flow. Me too. Hagen.

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STA and Simulation in a workflow
by Andreas Westerwick 29 May '18

29 May '18

Hello List, this question comes in two parts and is for hardware designers: In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow? The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow. Kind regards, Andreas Westerwick

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Status check: Test structures?
by David Lanzendörfer 29 May '18

29 May '18

Hi Hagen Any updates on the test structures already? Cheers David

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Results: Mumble Session on May 27, 2018
by David Lanzendörfer 28 May '18

28 May '18

Hi The following points resulted from yesterdays Mumble Session on May 27, 2018: We've discussed the need for a finalization of the test structure documentation in order to start drawing the test wafer layout. This task has been taken over by Hagen, please contact him if you wanna add more test structures or take over the task (would be very appreciated!) Hagen is also working on the first revision of the design rules document. My task is to finish the first process flow to test with the machines at HKUST. Also we've discussed attack vectors through JTAG in view of future highly secure SoCs with encrypted DRAM (crypto unit withint he DRAM controller) and I'm working out a paper on the side on that topic. All together I've got a pretty good solution to prevent attacks at running systems, which is to provide a reset pin which has to be toggled at least at the begging of the communication in order to set the device into "JTAG mode" which will reset the DRAM crypto key and make it impossible to extract data stored before switching into JTAG mode. (The DI, DO flipflop only is being clocked when the "JTAG mode" bit is true) Cheers David

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Test
by Andreas Westerwick 27 May '18

27 May '18

Hi Team

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next Mumble Session on May 27, 2018, 21.00 HKT
by Hagen SANKOWSKI 26 May '18

26 May '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, May 27 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - hackathon outcome - test wafer structures - other stuff around libre silicon Happy to hear from you! Hagen

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QtFlow Tool Chain Proposal
by Hagen SANKOWSKI 24 May '18

24 May '18

Hello List. As you might notice already, we hold a LibreSilicon Tool Chain Hackathon over the last weekend. Well, to get a impression, or a picture of our notes - please look at the attached JPG. For the more advanced stuff I draw a XML file with draw.io and got the also attached PDF. I think, this could inform new attendee about the topic, help to understand our design flow and even rule the tool development in future. Please give me feedback about the Tool Chain Proposal! Thanks! Best Regards, Hagen Sankowski P.S.: Thanks to Andreas who start to draw the flows for already existing tool suites.

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hallo
by Stefan Helmert 22 May '18

22 May '18

ich bin da

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