June 2019 - Libresilicon-developers

Status
by David Lanzendörfer 29 Jun '19

29 Jun '19

Hi everyone So the test run for increased polysilicon thickness in order to fix the leakage has been successful, as least from a visual point of view. The nitride spacer walls are now visible under the microscope. It just seems as if some idiot has put the wrong sputter source into the Titanium compartment for the NSC3000 which wouldn't have been a problem if the Varian sputterer wouldn't have spontaneously broken again on Thursday. So now, as with mystery meals, I have no idea what exactly is on those wafers. It's kind of reasonable that the film might be transparent, because of a different uniformity, but then again, it didn't dissolve in RCA-1 solution after more than 15 minutes, which makes the claim that it's "just a different etch rate" pretty much bollocks. However. Depositing more polysilicon (~300nm) seems like the way to go. I don't wanna use more, because the higher the poly-thickness, the bigger the resistance between the Poly-TiSi2 and the actual SiO2 dielectric, which impairs the frequency behavior of the FETs. It seems as if the folks have already processed our contract renewal, since I was able to log in on the NFF website and I'm able to book from Tuesday on upwards. I'll prepare 10 new wafers on Tuesday, where I'll etch the STI and deposit the first LTO load (4 microns), then CMP 15 minutes, BOE until silicon becomes visible, again LTO (2 microns), CMP again 10 minutes, which should remove parts of the Silicon and leave silicon islands surrounded by LTO. This way I can have a topology which isn't bigger than 200nm in dz (height difference) which will allow nicely connected polysilicon gates, with h=300nm And this time I take CKs advice and check every sputter source for the markings on the back (they scratched the material identifiers on the back he said) before depositing -lev

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Status update
by David Lanzendörfer 21 Jun '19

21 Jun '19

Hi everyone So today I've etched the gates. Took a bit longer, because the SVG coater just gave up on all of us this week. Henry repaired it to a degree where at least the HMDS priming and manual/auto dispense work again now, but the soft bake hotplate is fucked without hope. Next month they'll replace the SVG line with a new coater/developer track anyway, so no worries. Today Li Ho showed me the widget in the right bottom corner of the poly etcher control which actually tells me with a curve, as soon as the poly is gone by analyzing the color of the wafer which is directed from the top of the etching chamber to a chromometer with a glass fiber. I can't believe I've never noticed the ICP endpoint widget before! ^^' Anyway. Etching the poly took around 1.5 minutes for each wafer and I etched each wafer for 3 minutes, which will make sure, that there is no sidewall residue of the polysilicon left, which might cause shorts. The color of the isolating oxide between the junctions and the bulk is still blue-ish, which means, that it's still in the range of around 800-1000 Angstrom. (Addressing the concern from Ferenc) Monday I should be able to etch the 200nm LTO implant stop structures, perform the nimplan+pimplant and anneal it for 30 minutes at 900 degrees Celsius. After that I can form the nitride spacers, perform the silicide formation and add the wires. There shouldn't be shorts anymore now, this time. -lev

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IT fixup
by David Lanzendörfer 17 Jun '19

17 Jun '19

Hi folks I've now fixed the issue with the non-functional links in Mailman, as well as set up a Redmine with Gitolite integration. https://redmine.libresilicon.com/projects With Gitolite integration: https://redmine.libresilicon.com/projects/pearl-river/repository Here we can also track issues, and it's on my own server -lev

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Redmine
by David Lanzendörfer 16 Jun '19

16 Jun '19

Hi folks I've set up a redmine: https://redmine.libresilicon.com/projects[1] With Gitolite integration: https://redmine.libresilicon.com/projects/pearl-river/repository[2] Here we can also track issues, and it's on my own server -lev -------- [1] https://redmine.libresilicon.com/projects [2] https://redmine.libresilicon.com/projects/pearl-river/repository

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Anyone at the RISC-V developers workshop in Zürich?
by Christoph Maier 15 Jun '19

15 Jun '19

During my usual twitter procrastination, I stumbled across https://tmt.knect365.com/risc-v-workshop-zurich/agenda/1#risc-v-projects_ef… Where could I find links to the slides and the Raven chip information? Greetings from Tübingen, tatzelbrumm

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Re: [Libre-silicon-devel] Analog design toolchain for 555
by Éger Ferenc 06 Jun '19

06 Jun '19

Hello, Sorry, I forgot the link. It is im my git repo at https://github.com/eegerferenc/CMOS-555/tree/master/Tools/librarian Regards, Ferenc > > > > On Tue, Jun 4, 2019 at 6:02 PM Philipp Gühring <pg(a)futureware.at> wrote: > >> Hi, >> >> > The librarian tool (auto-generation of static magic library from spice >> > netlist) is out. Please check if it is useable. >> >> Where is that tool available? >> >> Best regards, >> Philipp >> >>

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The mailing list is back!
by David Lanzendörfer 06 Jun '19

06 Jun '19

Hi list While coughing my lungs out and eating paracetamol, so that I don't get high fever again, like last time with a flu, when I nearly died, I've been hacking around on upgrading the mail server. Good news! The mailing list is back! ;-) -lev

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test
by David Lanzendörfer 06 Jun '19

06 Jun '19

test

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test
by David Lanzendörfer 06 Jun '19

06 Jun '19

test

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test
by David Lanzendörfer 06 Jun '19

06 Jun '19

foo

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