Hi folks So Andreas and I were brain storming on how we could ensure the next years rent without relying solely on the private money of a few individuals and came up with the idea of a gofundme-campaign. Seems to work for a lot of people with much less important financial problems, so we figured, it's worth a shot. In case you've got some cash to spare, it would be fantastic if you could contribute a bit to our campaign goal. The more you help out, the less we've gotta stem privately from loans and so.
Also please share with everyone you know, in order to spread the message and help us finalize the PDK.
Even if lots of you folks are too busy to actively participate on the mailing list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
Here is the campaign link: https://www.gofundme.com/libresilicon-cleanroom-rent
Thanks David
On Sun, Apr 28, 2019 at 3:47 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Even if lots of you folks are too busy to actively participate on the mailing list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
i can emphasise that getting the word out to as many people as you can, and asking those friends to also pass on the link to their friends, reminding them as much as possible with as much "new stuff" as possible, on as many possible channels as possible, is the way to get a campaign to succeed.
david if you and the team can think of "new things to announce every few days", that gives you a reasonable (and non-repetitive) excuse to hit the communications network again and again, without irritating people immensely (and successfully getting through the social-media-overload phenomenon).
l.
Hi, are there chips that can be done quite quickly that have a market? So a 555 has no market as there are cheaper options. Chips need to be tested and packaged. But maybe there is an expensive chip that is not longer manufactured while there is a demand. I can only think of some IEEE488 controllers made by National Instruments for ISA bus, but there are USBtoIEEE488 adapters around based on micro controllers which seem to be good enough.
We need a chip that is lacking if it is missing it is a show stopper for some business / manufacturing machine.
Any ideas?
Cheers,
Ludwig
On Sun, Apr 28, 2019 at 3:25 PM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sun, Apr 28, 2019 at 3:47 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Even if lots of you folks are too busy to actively participate on the
mailing
list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
i can emphasise that getting the word out to as many people as you can, and asking those friends to also pass on the link to their friends, reminding them as much as possible with as much "new stuff" as possible, on as many possible channels as possible, is the way to get a campaign to succeed.
david if you and the team can think of "new things to announce every few days", that gives you a reasonable (and non-repetitive) excuse to hit the communications network again and again, without irritating people immensely (and successfully getting through the social-media-overload phenomenon).
l. _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hello,
"Hi, are there chips that can be done quite quickly that have a market?": I feel that the problem here is not the possible market: we are now in a very preliminarier-than-preliminary stage of chip-making and chip-design. The 555 was chosen as a target not only because of its symbolic perspective, but because this is what can be now done quickly with the knowledge, tooling and resources we have right now, and still can "blink and beep". For example, USBtoIEEE488 would require a USB device controller with significant complexity (data buffers, state machines, endpoint management), and implementing the USB stack needs at least a small MCU (that is complex in itself), not to mention the clock generation, clock-recovery PLLs, high-speeed transcievers etc. needed for USB PHY. Developing this would take at least months of simulation only for the logic (and maybe much more when we consider the analog and mixed-signal part, not to mention the validation...). And I'm pretty sure that implementing an USB device core on silicon will bring in the patent lawyers from USB-IF and virtually all IP core vendors...
Regards, Ferenc
On Sun, Apr 28, 2019 at 9:54 PM ludwig jaffe ludwig.jaffe@gmail.com wrote:
Hi, are there chips that can be done quite quickly that have a market? So a 555 has no market as there are cheaper options. Chips need to be tested and packaged. But maybe there is an expensive chip that is not longer manufactured while there is a demand. I can only think of some IEEE488 controllers made by National Instruments for ISA bus, but there are USBtoIEEE488 adapters around based on micro controllers which seem to be good enough.
We need a chip that is lacking if it is missing it is a show stopper for some business / manufacturing machine.
Any ideas?
Cheers,
Ludwig
On Sun, Apr 28, 2019 at 3:25 PM Luke Kenneth Casson Leighton < lkcl@lkcl.net> wrote:
On Sun, Apr 28, 2019 at 3:47 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Even if lots of you folks are too busy to actively participate on the
mailing
list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
i can emphasise that getting the word out to as many people as you can, and asking those friends to also pass on the link to their friends, reminding them as much as possible with as much "new stuff" as possible, on as many possible channels as possible, is the way to get a campaign to succeed.
david if you and the team can think of "new things to announce every few days", that gives you a reasonable (and non-repetitive) excuse to hit the communications network again and again, without irritating people immensely (and successfully getting through the social-media-overload phenomenon).
l. _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
My read on the larger free silicon community is there is a lot of skepticism that David and Hagen can pull off *any* chip but if they were to do so a wellspring of support and interest is to follow.
If the 555 chip is less then a dozen weeks away I would aim for a smaller GoFundMe to see it realized and capitalize on the excitement at that point to cover the next year of lab space.
To put my money where my mouth is I’m happy to contribute $1,000 to at least start the ball rolling.
-pmg
On Apr 29, 2019, at 11:04 AM, Éger Ferenc eegerferenc@gmail.com wrote:
Hello,
"Hi, are there chips that can be done quite quickly that have a market?": I feel that the problem here is not the possible market: we are now in a very preliminarier-than-preliminary stage of chip-making and chip-design. The 555 was chosen as a target not only because of its symbolic perspective, but because this is what can be now done quickly with the knowledge, tooling and resources we have right now, and still can "blink and beep". For example, USBtoIEEE488 would require a USB device controller with significant complexity (data buffers, state machines, endpoint management), and implementing the USB stack needs at least a small MCU (that is complex in itself), not to mention the clock generation, clock-recovery PLLs, high-speeed transcievers etc. needed for USB PHY. Developing this would take at least months of simulation only for the logic (and maybe much more when we consider the analog and mixed-signal part, not to mention the validation...). And I'm pretty sure that implementing an USB device core on silicon will bring in the patent lawyers from USB-IF and virtually all IP core vendors...
Regards, Ferenc
On Sun, Apr 28, 2019 at 9:54 PM ludwig jaffe ludwig.jaffe@gmail.com wrote: Hi, are there chips that can be done quite quickly that have a market? So a 555 has no market as there are cheaper options. Chips need to be tested and packaged. But maybe there is an expensive chip that is not longer manufactured while there is a demand. I can only think of some IEEE488 controllers made by National Instruments for ISA bus, but there are USBtoIEEE488 adapters around based on micro controllers which seem to be good enough.
We need a chip that is lacking if it is missing it is a show stopper for some business / manufacturing machine.
Any ideas?
Cheers,
Ludwig
On Sun, Apr 28, 2019 at 3:25 PM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote: On Sun, Apr 28, 2019 at 3:47 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Even if lots of you folks are too busy to actively participate on the mailing list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
i can emphasise that getting the word out to as many people as you can, and asking those friends to also pass on the link to their friends, reminding them as much as possible with as much "new stuff" as possible, on as many possible channels as possible, is the way to get a campaign to succeed.
david if you and the team can think of "new things to announce every few days", that gives you a reasonable (and non-repetitive) excuse to hit the communications network again and again, without irritating people immensely (and successfully getting through the social-media-overload phenomenon).
l. _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://secure-web.cisco.com/1kMwoBjfBwszMKW-xMFFlqYad2tayzHD4yd990ihN3MTyF3C...
Paul Gerhardt schreef op ma 29-04-2019 om 11:12 [-0700]: My read on the larger free silicon community is there is a lot of skepticism that David and Hagen can pull off *any* chip but if they were to do so a wellspring of support and interest is to follow.
You can count me as one of the skeptics. Although I am not one who claims it is not possible; with enough money and dedication it should be possible to get it done in a clean room that is already running a working process. Only I do think the amount of work and money needed is heavily underestimated and not with percentages but with real multiples to even an order of magnitude. And afterwards the process will still need a lot more development to get somewhere in the neighborhood in performance and cost of a current mature foundry node.
Also, on what is the statement on the go fund me campaign that the 555 timer is only a few weeks of based on ? Currently I only have seen a schematic posted and did not even see a diode characteristic of any junction in the process under development. I may be indoctrinated by too long being involved with clean room work. But to me such a statement seems to be totally unrealistic and i guess to anyone with micro-electronics clean room experience. IMHO, only real things that can be achieved should be on funding page.
greets, Staf.
Hi
My read on the larger free silicon community is there is a lot of skepticism that David and Hagen can pull off *any* chip but if they were to do so a wellspring of support and interest is to follow.
Also, on what is the statement on the go fund me campaign that the 555 timer is only a few weeks of based on ? Currently I only have seen a schematic posted and did not even see a diode characteristic of any junction in the process under development. I may be indoctrinated by too long being involved with clean room work. But to me such a statement seems to be totally unrealistic and i guess to anyone with micro-electronics clean room experience. IMHO, only real things that can be achieved should be on funding page.
We're now finalizing the first wafer with nitride spacers and have prepared two wafers with STI, which will be thermally compensated, so that the threshold voltage will be somewhere around the 0.7V/-0.7V threshold.
I'm not a quitter, and getting this node to work is more of an existential need for me, so if everything goes well, we can provide the diode and also a general NMOS/PMOS model on Friday in a week.
-lev
David Lanzendörfer schreef op wo 01-05-2019 om 11:02 [+0800]:
Hi
We're now finalizing the first wafer with nitride spacers and have prepared two wafers with STI, which will be thermally compensated, so that the threshold voltage will be somewhere around the 0.7V/-0.7V threshold.
I'm not a quitter, and getting this node to work is more of an existential need for me, so if everything goes well, we can provide the diode and also a general NMOS/PMOS model on Friday in a week.
Thing is that I have not seen any electrical measurements of any active device yet. What I have seen up to now is just some top down pictures; so my conclusion with the information I have is that currently the patterning is still being developed. When I was involved in process development the patterning development was the development step needed before the real process development could be started. Only from the moment I/V curves could be measured the real development of the devices could be started. I have never seen that implantation settings that come out of formulas/simulations were the right values from the start. Typically the first measured data were needed to re-calibrate the TCAD simulator :) and with the next iteration maybe some modulation was seen of the gate voltage on the output current... Of course we are now redoing mature nodes where things should be better understood but from the other side I seem to have understood the implantation doses, temperatures etc. were determined by generic formulas from literature and not with TCAD simulators calibrated with the characteristics of the materials and equipment inside the used clean room.
I admire you drive for getting this process working but I still think you have a lot to learn yet and a lot of development work ahead. So I still think the statement on the funding page is more wishful thinking than reality. I still remember the original plan of having ring oscillator working @ 35C3. I certainly don't want to stop you but would like to explain where (part of) the skepticism in the micro-electronics world is coming from.
greets, Staf.
Hello
Thing is that I have not seen any electrical measurements of any active device yet.
Yes. The first active devices should be functional mid of next week.
We had to figure out a proper way to form silicide and to interconnect the wires with the transistors. That was ground work and is basically done now. Resistor measurements will be done tomorrow...
And by measuring the transfer function of a transistor and storing it numerically into a file allows to create a SPICE model from it.
That's why I say, on Friday in a week we will most likely be able to provide the first models...
I think, the main reason why everyone is waiting for the project to run out of money or the people to walk away is rather, that established foundries, of which there are only a few, have not much interest into having another competitor. We had to research the things, the foundries keep a secret and worked the rest of the stuff out from scientific papers. Took a while, but because there is now a lot of literature, it's quicker than the first time around, when the first foundries had to figure it out from scratch.
-lev
On Wednesday, May 1, 2019, David Lanzendörfer < david.lanzendoerfer@lanceville.cn> wrote:
. We had to research the things, the foundries keep a secret and worked the rest of the stuff out from scientific papers. Took a while, but because there is now a lot of literature, it's quicker than the first time around, when the first foundries had to figure it out from scratch.
This is one of the key lessons that I learned from reverse engineering. Do NOT be tempted to innovate or deviate IN ANY WAY until the task is completed.
It sounds boring, you want to do something new, be the innovator! but is incredibly important NOT to do so.
Now you know why I recommended the 6502 not say the 6510, because the full lithographic masks of the 6502 have been rev/engd and the netlist created, to the point where there is now an online OPERATIONAL javascript 6502 simulator.
Hagen's suggestion of doing the IO ASIC, just as goid, because the verilog source is available.
Hi
This is one of the key lessons that I learned from reverse engineering. Do NOT be tempted to innovate or deviate IN ANY WAY until the task is completed.
It sounds boring, you want to do something new, be the innovator! but is incredibly important NOT to do so.
Now you know why I recommended the 6502 not say the 6510, because the full lithographic masks of the 6502 have been rev/engd and the netlist created, to the point where there is now an online OPERATIONAL javascript 6502 simulator.
Hagen's suggestion of doing the IO ASIC, just as goid, because the verilog source is available.
Oh. We went into the R&D with a clear plan on the overall order of steps and a basic procedure, derived from older 1um processes and lots of literature.
Then, in the lab, some chemical reactions (mainly silicide formation) did not work as expected, so we had to go back to the drawing board and figure silicide and interconnet with silicide out.
In overall, I've got a very good idea on what I'm doing and where I'm standing.
The problem is more, that we need to make sure, that we can actually produce products with the process, I'm basically done figuring out now.
... Well. At least the NMOS/PMOS have no more issues left, which would stop it from switching next week, so it would really surprise me, if this still wouldn't work...
The implications of an open node are so big, that it's unacceptable not to finish.
We're in a marathon, and I can finally see the finish line, would be shit to quit on the last few meters...
-lev
David, very brave work you do. We should find a business case to be able to collect money on a crowd funding platform like kickstarter.com
So we *need* a product and a road map. The product needs to be catchy and address needs of a geek. So as I wrote today, I strongly suggest building C64 spares, beginning with the CIA-peripheral, as peripherals get broken most likely as they are exposed to experimentation, e.g. user port.
How to package, do we have access to a package molding company or package molding tools, in order to put our chips into a nice DIL40 package https://www.c64-wiki.com/wiki/CIA http://www.6502.org/documents/datasheets/mos/ We can by a C64 and do reverse engineering by grinding and photographing the layers of the chips if needed. http://www.degate.org/documentation/
Lets do DIL40 stuff first, as I think there is some quite easy money :-)
Cheers ludwig
On Wed, May 1, 2019 at 9:05 AM David Lanzendörfer < david.lanzendoerfer@lanceville.cn> wrote:
Hello
Thing is that I have not seen any electrical measurements of any active device yet.
Yes. The first active devices should be functional mid of next week.
We had to figure out a proper way to form silicide and to interconnect the wires with the transistors. That was ground work and is basically done now. Resistor measurements will be done tomorrow...
And by measuring the transfer function of a transistor and storing it numerically into a file allows to create a SPICE model from it.
That's why I say, on Friday in a week we will most likely be able to provide the first models...
I think, the main reason why everyone is waiting for the project to run out of money or the people to walk away is rather, that established foundries, of which there are only a few, have not much interest into having another competitor. We had to research the things, the foundries keep a secret and worked the rest of the stuff out from scientific papers. Took a while, but because there is now a lot of literature, it's quicker than the first time around, when the first foundries had to figure it out from scratch.
-lev_______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
at luke kenneth: " This is one of the key lessons that I learned from reverse engineering. Do NOT be tempted to innovate or deviate IN ANY WAY until the task is completed.
It sounds boring, you want to do something new, be the innovator! but is incredibly important NOT to do so.
Now you know why I recommended the 6502 not say the 6510, because the full lithographic masks of the 6502 have been rev/engd and the netlist created, to the point where there is now an online OPERATIONAL javascript 6502 simulator.
Hagen's suggestion of doing the IO ASIC, just as goid, because the verilog source is available. " Wise words, you are right. So the 6502 is first as it is easy game because others revered it already. But then I suggest to reverse commodore stuff, to gain a community of commodore boys who want spares. http://www.6502.org/documents/datasheets/mos/
To do that I suggest grinding. https://fahrplan.events.ccc.de/congress/2008/Fahrplan/attachments/1218_08122... http://www.degate.org/documentation/
Cheers,
Ludwig
On Wed, May 1, 2019 at 10:44 AM ludwig jaffe ludwig.jaffe@gmail.com wrote:
David, very brave work you do. We should find a business case to be able to collect money on a crowd funding platform like kickstarter.com
So we *need* a product and a road map. The product needs to be catchy and address needs of a geek. So as I wrote today, I strongly suggest building C64 spares, beginning with the CIA-peripheral, as peripherals get broken most likely as they are exposed to experimentation, e.g. user port.
How to package, do we have access to a package molding company or package molding tools, in order to put our chips into a nice DIL40 package https://www.c64-wiki.com/wiki/CIA http://www.6502.org/documents/datasheets/mos/ We can by a C64 and do reverse engineering by grinding and photographing the layers of the chips if needed. http://www.degate.org/documentation/
Lets do DIL40 stuff first, as I think there is some quite easy money :-)
Cheers ludwig
On Wed, May 1, 2019 at 9:05 AM David Lanzendörfer < david.lanzendoerfer@lanceville.cn> wrote:
Hello
Thing is that I have not seen any electrical measurements of any active device yet.
Yes. The first active devices should be functional mid of next week.
We had to figure out a proper way to form silicide and to interconnect the wires with the transistors. That was ground work and is basically done now. Resistor measurements will be done tomorrow...
And by measuring the transfer function of a transistor and storing it numerically into a file allows to create a SPICE model from it.
That's why I say, on Friday in a week we will most likely be able to provide the first models...
I think, the main reason why everyone is waiting for the project to run out of money or the people to walk away is rather, that established foundries, of which there are only a few, have not much interest into having another competitor. We had to research the things, the foundries keep a secret and worked the rest of the stuff out from scientific papers. Took a while, but because there is now a lot of literature, it's quicker than the first time around, when the first foundries had to figure it out from scratch.
-lev_______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
On Wed, 2019-05-01 at 10:44 -0400, ludwig jaffe wrote:
David, very brave work you do. We should find a business case to be able to collect money on a crowd funding platform like kickstarter.com
So we *need* a product and a road map. The product needs to be catchy and address needs of a geek.
Hi !
I am very new to this group, so please forgive if I am asking something that has been discussed already.
1. Do you guys have a standard cell library for this fab ?
2. Whats the smallest features size that can be supported ?
3. Can this chip be mixed analog/digital ?
4. Do you have any IP for this fab, like a SERDES for example ?
5. Is there any NRE ?
6. What is the wafer size ?
7. What is the wafer cost ?
8. Is there a die size limit ?
9. What packaging is available to you ?
I am trying to grasp what the boundaries of our imagination should be for proposing a "test chip".
I think it can be very easy to get funding for the right chip.
Best Regards, rudi =============================================================== Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
The agony of poor quality remains long after the joy of low cost has been forgotten
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Hello Rudolf!
Comments inside.
On 5/1/19 5:06 PM, Rudolf Usselmann wrote:
I am very new to this group, so please forgive if I am asking something that has been discussed already.
No problem. Thanks for joining our mailing list and a warm welcome :-)
- Do you guys have a standard cell library for this fab ?
Still not, but I am working hard on that. The repository you'll find here
https://github.com/chipforge/StdCellLib
- Whats the smallest features size that can be supported ?
We currently targeting 1 micron, but the equipment we are using is able to handle 500 nm also.
- Can this chip be mixed analog/digital ?
Yes, definitively, that's what we aimed for. https://github.com/libresilicon/process
- Do you have any IP for this fab, like a SERDES for example ?
No. Regarding our feature size of 1 micron this is a little bit far ahead.
- Is there any NRE ?
It's up to you. All information you'll need is public. You can hire someone to do the job for you, or doing it by yourself. In the end, the Masks have to be done.
- What is the wafer size ?
The Clean Room we are using has equipment for 4 inches, as well as 5 or 6 for some machines. So mainly 4 inches.
- What is the wafer cost ?
Depends on condition / preparation between 10 and 20 bucks for 4 inches. http://www.nff.ust.hk/en/our-services/charging-scheme.html
- Is there a die size limit ?
Well, regarding the clean room conditions, there is a probability that with rising die size statistically on every die at least one piece of dust is causing defects. Your yields goes down to zero.
Better your die size is still small enough to be "between" two pieces of dust. At 10.000 class clean rooms, practically the limit is somewhere around 10 by 10 mm.
If the die size is small enough (as our Test Chip less than 5 x 5 mm) you can safe money by sharing the mask for 4 mask layers.
- What packaging is available to you ?
We not fully evaluate this topic with the lab which will do the packaging for us - assume all the older, quite saturated packages up to flip-chip BGA.
I am trying to grasp what the boundaries of our imagination should> be for proposing a "test chip".
David is currently processing this Test Chip - https://github.com/chipforge/PearlRiver
We collect there a lot of different circuits, like MOSFETs, Resistors, Capacities, Diodes, BJT and even Ring Oscillators with some Standard Cells (NAND3, NOR3 and INV) each with pads around for (mostly) 4-point measurements.
I think it can be very easy to get funding for the right chip.
Any suggestions?
Best Regards, Hagen.
=============================================================== Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
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On Wed, 2019-05-01 at 17:55 +0200, Hagen SANKOWSKI wrote:
Hello Rudolf!
Comments inside.
Thank you for the quick reply Hagen !
I think it can be very easy to get funding for the right chip.
Any suggestions?
Here are a few thoughts ....
Soooo, 1 micron is much larger than I hoped for!
I took a quick look at the standard cell library. Looks like no flops or latches so far. I wonder if the generated library can be used with Synopsys DC.
I think you need a few more items before making a commercial chip:
1. Flip Flops (with and without scan support) 2. Latches 3. Gates should have at least 3 different drive strength 4. True 2T SRAM (memory compiler) 5. FLASH memory 6. programmable PLL
It would be interesting to know what the max frequency for a 32 bit MAC would be (input and output registers only), and what kind of power consumption to expect.
Almost any chip you make will need to be low power - this is where everything moves these days.
In my opinion, a 555 will have zero commercial value. You'll have to make sure the electrical characteristics match whats out there, or it will not be compatible.
I'm not sure if you guys are just looking for some educational fun and proof of concept, or really want to make something you can sell.
I think once you have the above listed components, you can seriously consider making something that can make money.
I would recommend that you try to integrate the above items in your test chip.
Also, I am still curious to find out more about the cost:
10 cm wafer would get you about 200 x 25 sqmm dies. Assuming 80% yield you'll end up with about 160 good dies. That's about $0.125 USD for the dies. 25 sqmm is a very small chip for 1um.
How much will it cost to cut the wafer and package the dies in some tssop/soic or similar package ?
What are the actual mask costs if you guys do them yourself ?
How about testing the final chips ? Do they have test equipment that is fully automatic and can test several thousend chips in a run ? How about binning is that supported ?
What other costs are there ?
And most importantly, if you want to make a commercial chip, what is the FAB capacity ? If you want to run 10K wafers, or 100k wafers will they let you ?
rudi =============================================================== Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
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Hello Rudolf.
On 5/2/19 10:21 AM, Rudolf Usselmann wrote:
On Wed, 2019-05-01 at 17:55 +0200, Hagen SANKOWSKI wrote:
Hello Rudolf!
Comments inside.
Thank you for the quick reply Hagen !
Well, decades ago I keep track on opencores.org - and among all the students project there your code / cores were in the best shape and code quality. I learned while reading your code. Thank you!
Here are a few thoughts ....
Soooo, 1 micron is much larger than I hoped for!
Yes, 1 micron does not sounds very ambitious, but this is the last node which is more or less completely documented in the textbooks. With smaller nodes the NDA-foo was disturbing the publication. Some aspects you'll find in the literature, but not all.
But 1 micron is perfect for analog stuff. All the analog MOSFETs have huge sizes for driving current.
Our advantage against the original 1 micron node is, that fabs do not touch the old nodes, do not advanced them with STI or LTO. So we use techniques which came up later and insert them also into the "old" 1 micron. We guess becoming much better for the node than the original one.
Regarding the "big" feature size, a 1 Micron fits better the needs for harsh environment, radiation and space exploration. The temperature range can be extended. Also the supply power hasn't to be such accurate and stable. 1 Micron better plays with supply voltages between 3 and let's say 40 Volt e.g. for automotive. Of course, the 5 Volt support for all the tinkerer and maker in their basement is not a problem.
And once up and running, we can jump further to 0.5 Micron, the machinery equipment is the same.
I took a quick look at the standard cell library. Looks like no flops or latches so far. I wonder if the generated library can be used with Synopsys DC.
The Library is still Work-in-Progress. Since the library development is a one-man-show, it is not feasible to draw *all* cells by hand. Last year I started and it took me something between one and two weeks for only one cell. So estimating a cell count of 400, I decide to stop hand-crafting all the cells and write a Cell Generator instead. Unfortunately I am not a programmer, so it also took me effort to do so. But, yeah, now I see progress in coding the cell generator, which I called "Popcorn".
I think you need a few more items before making a commercial chip:
- Flip Flops (with and without scan support)
- Latches
Yes, on the list.
- Gates should have at least 3 different drive strength
Regarding the driving current, the last transistor stage has to become quite huge, or, you add another buffer with different strength. In this case, it could also be up to the synthesis tool to buffer up higher fan-ins or longer lines.
I decide, to draw (smaller) cells with one unified fan-out only and let the tools do the rest.
- True 2T SRAM (memory compiler)
Yes, on the list.
- FLASH memory
The PearlRiver (Test Wafer) already has some flash cells. They are still not evaluated.
- programmable PLL
PLLs are analog stuff. In lack of the right guy to do so, we first add Ring Oscillators in to the PearlRiver.
It would be interesting to know what the max frequency for a 32 bit MAC would be (input and output registers only), and what kind of power consumption to expect.
Almost any chip you make will need to be low power - this is where everything moves these days.
Yes, our aim to squeeze 1 Micron in this direction.
In my opinion, a 555 will have zero commercial value. You'll have to make sure the electrical characteristics match whats out there, or it will not be compatible.
I'm not sure if you guys are just looking for some educational fun and proof of concept, or really want to make something you can sell.
I think once you have the above listed components, you can seriously consider making something that can make money.
I would recommend that you try to integrate the above items in your test chip.
You can look, what is already on the PearlRiver. Currently in Magic, the documentation is unfortunately still not complete.
Also, I am still curious to find out more about the cost:
10 cm wafer would get you about 200 x 25 sqmm dies. Assuming 80% yield you'll end up with about 160 good dies. That's about $0.125 USD for the dies. 25 sqmm is a very small chip for 1um.
How much will it cost to cut the wafer and package the dies in some tssop/soic or similar package ?
What are the actual mask costs if you guys do them yourself ?
One Mask was around 125 $ if I remember right. Depending on the technology features you like to use there are up to 18 (?) masks. This details David better know than me.
How about testing the final chips ? Do they have test equipment that is fully automatic and can test several thousend chips in a run ? How about binning is that supported ?
No. This is still a topic we have to solve. The lab has 4-point-Tester, but need manual effort to adjust the probes. Fully automatic stuff costs always the adapter plate for some thousands bucks.
What other costs are there ?
Well, we developing the technology in a University Lab and maintain some contacts to a regular Fab which is willing to adapt our process on their machines. Assuming we are successfully and can adapt the process to more fabs, the price becomes competitive.
And most importantly, if you want to make a commercial chip, what is the FAB capacity ? If you want to run 10K wafers, or 100k wafers will they let you ?
Once we got from the mentioned fab above an offer for 25k Waver per Month, regarding a normal yield this are 4M up to 20M Dies per Month.
Hard to sale, isn't it?
Best Regard, Hagen.
=============================================================== Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
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Hi Eger,
you got me wrong. My point was not designing a usb to HPIB alias IEE488 bridge.
My point was to do the vintage IEE488 controller used in ISA bus cards and old measurement equipment. So if the chip is gone the instrument cant be used with IEE488. So people pay lets say $100 to get a replacement chip that exactly behaves like the old. So chip brokers trading old stock get rich. Rebuilding old chips has the advantage that they are quite simple and on the other side valuable as nobody builds them. The Signetics NE555 is such an old chip but there is a big market so many fabs build replicas. So having a chip that has people with budget asking for it but no fab to build it is a good source of money, especially if one can sell small quantities at a high price. Lets look for such a candidate.
Cheers
Ludwig
On Monday, April 29, 2019, Éger Ferenc eegerferenc@gmail.com wrote:
Hello, "Hi, are there chips that can be done quite quickly that have a market?":
I feel that the problem here is not the possible market: we are now in a very preliminarier-than-preliminary stage of chip-making and chip-design. The 555 was chosen as a target not only because of its symbolic perspective, but because this is what can be now done quickly with the knowledge, tooling and resources we have right now, and still can "blink and beep". For example, USBtoIEEE488 would require a USB device controller with significant complexity (data buffers, state machines, endpoint management), and implementing the USB stack needs at least a small MCU (that is complex in itself), not to mention the clock generation, clock-recovery PLLs, high-speeed transcievers etc. needed for USB PHY. Developing this would take at least months of simulation only for the logic (and maybe much more when we consider the analog and mixed-signal part, not to mention the validation...). And I'm pretty sure that implementing an USB device core on silicon will bring in the patent lawyers from USB-IF
and virtually all IP core vendors... Regards, Ferenc
On Sun, Apr 28, 2019 at 9:54 PM ludwig jaffe ludwig.jaffe@gmail.com
wrote:
Hi, are there chips that can be done quite quickly that have a market? So a 555 has no market as there are cheaper options. Chips need to be tested and packaged. But maybe there is an expensive chip that is not longer manufactured while there is a demand. I can only think of some IEEE488 controllers made by National Instruments for ISA bus, but there are USBtoIEEE488 adapters around based on micro controllers which seem to be good enough.
We need a chip that is lacking if it is missing it is a show stopper for some business / manufacturing machine.
Any ideas?
Cheers,
Ludwig
On Sun, Apr 28, 2019 at 3:25 PM Luke Kenneth Casson Leighton <
lkcl@lkcl.net> wrote:
On Sun, Apr 28, 2019 at 3:47 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Even if lots of you folks are too busy to actively participate on the
mailing
list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
i can emphasise that getting the word out to as many people as you can, and asking those friends to also pass on the link to their friends, reminding them as much as possible with as much "new stuff" as possible, on as many possible channels as possible, is the way to get a campaign to succeed.
david if you and the team can think of "new things to announce every few days", that gives you a reasonable (and non-repetitive) excuse to hit the communications network again and again, without irritating people immensely (and successfully getting through the social-media-overload phenomenon).
l. _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hi Eger,
you got me wrong. My point was not designing a usb to HPIB alias IEE488 bridge.
My point was to do the vintage IEE488 controller used in ISA bus cards and old measurement equipment. So if the chip is gone the instrument cant be used with IEE488. So people pay lets say $100 to get a replacement chip that exactly behaves like the old. So chip brokers trading old stock get rich. Rebuilding old chips has the advantage that they are quite simple and on the other side valuable as nobody builds them. The Signetics NE555 is such an old chip but there is a big market so many fabs build replicas. So having a chip that has people with budhet asking for it but no fab to build it is a good source of money especially if one can sell small quantities at a high price. Lets look for such a candidate.
Cheers
Ludwig
On Monday, April 29, 2019, Éger Ferenc eegerferenc@gmail.com wrote:
Hello, "Hi, are there chips that can be done quite quickly that have a market?":
I feel that the problem here is not the possible market: we are now in a very preliminarier-than-preliminary stage of chip-making and chip-design. The 555 was chosen as a target not only because of its symbolic perspective, but because this is what can be now done quickly with the knowledge, tooling and resources we have right now, and still can "blink and beep". For example, USBtoIEEE488 would require a USB device controller with significant complexity (data buffers, state machines, endpoint management), and implementing the USB stack needs at least a small MCU (that is complex in itself), not to mention the clock generation, clock-recovery PLLs, high-speeed transcievers etc. needed for USB PHY. Developing this would take at least months of simulation only for the logic (and maybe much more when we consider the analog and mixed-signal part, not to mention the validation...). And I'm pretty sure that implementing an USB device core on silicon will bring in the patent lawyers from USB-IF
and virtually all IP core vendors... Regards, Ferenc
On Sun, Apr 28, 2019 at 9:54 PM ludwig jaffe ludwig.jaffe@gmail.com
wrote:
Hi, are there chips that can be done quite quickly that have a market? So a 555 has no market as there are cheaper options. Chips need to be tested and packaged. But maybe there is an expensive chip that is not longer manufactured while there is a demand. I can only think of some IEEE488 controllers made by National Instruments for ISA bus, but there are USBtoIEEE488 adapters around based on micro controllers which seem to be good enough.
We need a chip that is lacking if it is missing it is a show stopper for some business / manufacturing machine.
Any ideas?
Cheers,
Ludwig
On Sun, Apr 28, 2019 at 3:25 PM Luke Kenneth Casson Leighton <
lkcl@lkcl.net> wrote:
On Sun, Apr 28, 2019 at 3:47 PM David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Even if lots of you folks are too busy to actively participate on the
mailing
list, this is a chance to contribute something to the project. And it's only a few minutes of your time.
i can emphasise that getting the word out to as many people as you can, and asking those friends to also pass on the link to their friends, reminding them as much as possible with as much "new stuff" as possible, on as many possible channels as possible, is the way to get a campaign to succeed.
david if you and the team can think of "new things to announce every few days", that gives you a reasonable (and non-repetitive) excuse to hit the communications network again and again, without irritating people immensely (and successfully getting through the social-media-overload phenomenon).
l. _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
On Tuesday, April 30, 2019, ludwig jaffe ludwig.jaffe@gmail.com wrote:
. So having a chip that has people with budhet asking for it but no fab to build it is a good source of money especially if one can sell small quantities at a high price.
Sounds exactly like any entrepreneurial sales strategy I have ever heard.
Going a little more upscale, more than just a 555, is NEOther 8/16 bit processor supported by sdcc.
That's quite a big list, the most iconic of all would be the 6502.
The number of iconic computers that used it is off the charts. That's a big retro market right there.
Compiler: cc65 or something like that (google 6502 sdcc it comes up)
And what is particularly awesome is, its been reverse engineered http://visual6502.org/wiki/index.php?title=The_reverse_engineering_process
Turns out that the 6502 is a superscalar design! (wtf??)
:)
Guy who made it literally did the entire layout in his head, then drew out some masks on paper, blew them up to 1m sq, and hand dug out the lithographic masks from 1sq m pieces of linoleum!
Amazing story, totally iconic. Backstory like that will generate huge interest and PR that is precisely the kind of wow factor that allows it to go viral on social media.
"Hey look what I found, these crazy ppl r redoin the 6502, totally retro, an the real version wuz done by hand on lino, no software CAD tools at all, wtf, lolz"
:)
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Éger Ferenc