Hi One of the new faces at the table started to draw together an ADC with Magic. What's the status there?
Cheers David
Hello.
On 1/2/19 11:46 AM, David Lanzendörfer wrote:
One of the new faces at the table started to draw together an ADC with Magic. What's the status there?
It's tatzelbrumm, our interpreter EN->DE from the talk. He is already on the mailing list. I'll contact him.
Regards, Hagen.
Setting up lines of communication <mumble mumble> and refreshing memories <Hasler [Pronouns: she, her], Diorio, Minch>(remember those, Mr. Potbox?) <SONOS> in order to get involved and productive.
tatzelbrumm
On Wed, Jan 2, 2019 at 11:54 AM Hagen SANKOWSKI hsank@posteo.de wrote:
Hello.
On 1/2/19 11:46 AM, David Lanzendörfer wrote:
One of the new faces at the table started to draw together an ADC with Magic. What's the status there?
It's tatzelbrumm, our interpreter EN->DE from the talk. He is already on the mailing list. I'll contact him.
Regards, Hagen.
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hello Christoph a.k.a. Tatzelbrumm:
Setting up lines of communication <mumble mumble> and refreshing memories <Hasler [Pronouns: she, her], Diorio, Minch>(remember those, Mr. Potbox?) <SONOS> in order to get involved and productive.
I have not been in contact with Jen Hasler since the early 2000s, but I have been in touch with one of her associates previously at Georgia Tech, Brian "Degs" Degnan, who was involved in the first customer taped-out design from efabless (currently in fab). Chris Diorio, I have not heard from since the late 1990s. Brad Minch still occasionally exchanges emails with me about various EDA tool issues.
If it's possible to design an ADC in the Libre-Silicon process, then maybe it's time to start discussing onboarding the process on the efabless design platform. ---Tim
+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Hi Tim,
On Wed, Jan 2, 2019 at 2:15 PM Tim Edwards tim@opencircuitdesign.com wrote:
Hello Christoph a.k.a. Tatzelbrumm:
Setting up lines of communication <mumble mumble> and refreshing memories <Hasler [Pronouns: she, her], Diorio, Minch>(remember those, Mr. Potbox?) <SONOS> in order to get involved and productive.
I have not been in contact with Jen Hasler since the early 2000s, but I have been in touch with one of her associates previously at Georgia Tech, Brian "Degs" Degnan, who was involved in the first customer taped-out design from efabless (currently in fab). Chris Diorio, I have not heard from since the late 1990s. Brad Minch still occasionally exchanges emails with me about various EDA tool issues.
I was just thinking about some non-standard analog structures one might try out on the Pearl River process (speaking of, I had some AFGAs on AMS CXE or some such and tested/fried them when visiting newly established assistant professor PAUL Hasler at Georgia Tech in 2000).
If it's possible to design an ADC in the Libre-Silicon process, then maybe it's time to start discussing onboarding the process on the efabless design platform.
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
TTYL soon Christoph
---Tim+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Hello Christoph,
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
I have thought about this much less than you seem to think. I have never built up a fabrication process from scratch like the Libre Silicon guys. So test structures that go in the margins of wafers are things that I have a basic understanding of, but I am more familiar with analyzing the measurement results than with thinking about how the structures should be designed and how to make the measurements in the first place.
Best capacitor matching for ADCs generally comes from MiM capacitors, 2nd best from poly-poly capacitors, and for smaller feature sizes where the layer thickness is on par with the metal width and spacing rules, fingered MoM caps are probably 3rd best. Common centroid geometry with dummy devices on the periphery is a must. Beyond that, it really depends on what's being offered in the process.
ADC topology depends more on the application than anything else. My preference is Sigma-delta with digital filtering, but sometimes an SAR is called for. I've never seen anyone do flash ADCs in practice.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
Actually, no, efabless is not funded by venture capital. We are currently funded by a group of three people, one of whom is the CEO (Mike Wishart) and the other two long-time Silicon Valley startup founder types (Lucio Lanza and Jack Hughes). We are looking for additional investment from companies who can benefit from having IP in our catalog listings, or benefit from the web-based collaboration tools.
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
I am always happy to answer questions. Users are the lifeblood of open source tools, and must be kept happy. . .
Regards, Tim
+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Hi all,
we should prototype all kinds of components, capacitors, resistors, bipolar transistors and mos transistors, in order to get a protfolio of parts, there parts need to be identified, so we get a spice model for them. Remember, all parts are analog, even nand gates. You can use 4000 cmos logic to build bad amplifiers, just by having feedback resistors likewise with op amps.
So the process guys should try to make as many as possible parts on a wafer to get a parts lib.
Then we can build circuits like SAR or Delta Sigma ADC. A flash ADC with 8 bit would be funny but not that fast, but why not.
And always remember, our chips are not the fastest but the biggest :-)
Cheers,
Ludwig
On Wed, Jan 2, 2019 at 2:57 PM Tim Edwards tim@opencircuitdesign.com wrote:
Hello Christoph,
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
I have thought about this much less than you seem to think. I have never built up a fabrication process from scratch like the Libre Silicon guys. So test structures that go in the margins of wafers are things that I have a basic understanding of, but I am more familiar with analyzing the measurement results than with thinking about how the structures should be designed and how to make the measurements in the first place.
Best capacitor matching for ADCs generally comes from MiM capacitors, 2nd best from poly-poly capacitors, and for smaller feature sizes where the layer thickness is on par with the metal width and spacing rules, fingered MoM caps are probably 3rd best. Common centroid geometry with dummy devices on the periphery is a must. Beyond that, it really depends on what's being offered in the process.
ADC topology depends more on the application than anything else. My preference is Sigma-delta with digital filtering, but sometimes an SAR is called for. I've never seen anyone do flash ADCs in practice.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
Actually, no, efabless is not funded by venture capital. We are currently funded by a group of three people, one of whom is the CEO (Mike Wishart) and the other two long-time Silicon Valley startup founder types (Lucio Lanza and Jack Hughes). We are looking for additional investment from companies who can benefit from having IP in our catalog listings, or benefit from the web-based collaboration tools.
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
I am always happy to answer questions. Users are the lifeblood of open source tools, and must be kept happy. . .
Regards, Tim+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+ _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
On Wed, Jan 2, 2019, 15:40 ludwig jaffe <ludwig.jaffe@gmail.com wrote:
Hi all,
we should prototype all kinds of components, capacitors, resistors, bipolar transistors and mos transistors, in order to get a protfolio of parts, there parts need to be identified, so we get a spice model for them. Remember, all parts are analog, even nand gates. You can use 4000 cmos logic to build bad amplifiers, just by having feedback resistors likewise with op amps.
So the process guys should try to make as many as possible parts on a wafer to get a parts lib.
Then we can build circuits like SAR or Delta Sigma ADC. A flash ADC with 8 bit would be funny but not that fast, but why not.
And always remember, our chips are not the fastest but the biggest :-)
Unless one or two of us here have a neuromorphic / translinear circuit bucket list and access to bespoke process parameters, right, Mr. Potbox?
Tatzelbrumm
Cheers,
Ludwig
On Wed, Jan 2, 2019 at 2:57 PM Tim Edwards tim@opencircuitdesign.com wrote:
Hello Christoph,
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
I have thought about this much less than you seem to think. I have never built up a fabrication process from scratch like the Libre Silicon guys. So test structures that go in the margins of wafers are things that I have a basic understanding of, but I am more familiar with analyzing the measurement results than with thinking about how the structures should be designed and how to make the measurements in the first place.
Best capacitor matching for ADCs generally comes from MiM capacitors, 2nd best from poly-poly capacitors, and for smaller feature sizes where the layer thickness is on par with the metal width and spacing rules, fingered MoM caps are probably 3rd best. Common centroid geometry with dummy devices on the periphery is a must. Beyond that, it really depends on what's being offered in the process.
ADC topology depends more on the application than anything else. My preference is Sigma-delta with digital filtering, but sometimes an SAR is called for. I've never seen anyone do flash ADCs in practice.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
Actually, no, efabless is not funded by venture capital. We are currently funded by a group of three people, one of whom is the CEO (Mike Wishart) and the other two long-time Silicon Valley startup founder types (Lucio Lanza and Jack Hughes). We are looking for additional investment from companies who can benefit from having IP in our catalog listings, or benefit from the web-based collaboration tools.
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
I am always happy to answer questions. Users are the lifeblood of open source tools, and must be kept happy. . .
Regards, Tim+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+ _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hello Ludwig, Hello List!
On 1/2/19 3:39 PM, ludwig jaffe wrote:
we should prototype all kinds of components, capacitors, resistors, bipolar transistors and mos transistors, in order to get a protfolio of parts, there parts need to be identified, so we get a spice model for them.
Which else do you like?
Take a look at PearlRiver - this are all the structures we currently have.
https://github.com/chipforge/PearlRiver/tree/master/Library/magic
Do you missing something, eg. for analog Voodoo? Please provide :-) I am very happy to see more.
Regards, Hagen.
Question to Tim:
On Wed, Jan 2, 2019 at 3:40 PM ludwig jaffe ludwig.jaffe@gmail.com wrote:
Hi all,
we should prototype all kinds of components, capacitors, resistors, bipolar transistors and mos transistors, in order to get a protfolio of parts, there parts need to be identified, so we get a spice model for them.
Have you ever used the EKV model for a transistor design? Would a bespoke not deep submicron process be a good candidate as proof-of-concept for EKV?
Trying to split totally crazy from crazy but feasible ideas Christoph
Hello Christoph,
Have you ever used the EKV model for a transistor design?
Yes I have, but not for many years, since the early days of doing subthreshold designs and finding that the exising MOS models were discontinuous between the subthreshold and square-law regimes. Since the bsim3 models largely cured that problem, I have been satisfied with using vendor device models.
Would a bespoke not deep submicron process be a good candidate as proof-of-concept for EKV?
I would assume so. Regards, Tim
+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Can I make a special request to include a T gate (transmission gate) in that list as it is a critical and little understood component of an efficient NxN crossbar.
Matrix form not butterfly style.
Butterfly style crossbar is much higher number of gates than a T Gate style crossbar.
Also T gates make for significantly reduced logic cells although voltage is lost at each stage, buffers fix that.
https://en.m.wikipedia.org/wiki/Transmission_gate
On Thu, Jan 3, 2019 at 1:41 AM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
Can I make a special request to include a T gate (transmission gate) in that list as it is a critical and little understood component of an efficient NxN crossbar.
Analog switches are also an important building block for any kind of switched capacitor discrete time analog filters.
Matrix form not butterfly style. Butterfly style crossbar is much higher number of gates than a T Gate style crossbar.
Can you reference to circuit diagrams that explain what "matrix form" and "butterfly stlye" might mean?
Also T gates make for significantly reduced logic cells although voltage is lost at each stage, buffers fix that. https://en.m.wikipedia.org/wiki/Transmission_gate
Quite a few nonstandard digital cell designs exist and can be used to simplify a circuit, but definitely not the design process, because you need to know when to use them and when not to use them.
Christoph
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Jan 3, 2019 at 2:32 AM Christoph Maier christoph.maier@ieee.org wrote:
On Thu, Jan 3, 2019 at 1:41 AM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
Can I make a special request to include a T gate (transmission gate) in that list as it is a critical and little understood component of an efficient NxN crossbar.
Analog switches are also an important building block for any kind of switched capacitor discrete time analog filters.
Matrix form not butterfly style. Butterfly style crossbar is much higher number of gates than a T Gate style crossbar.
Can you reference to circuit diagrams that explain what "matrix form" and "butterfly stlye" might mean?
https://en.wikipedia.org/wiki/Butterfly_network
the picture there is a half-butterfly. mirror-image it and you have a full butterfly network.
my 3rd year project was an expansion of the ALICE transputer network, and i developed an algorithm that guaranteed 100% throughput on 100% of all permutations of inputs-to-outputs (no contention allowed), in a set linear time.
so i *know* for a fact that you can use a full butterfly network as a substitute for a full N-to-N crossbar (if prepared to tolerate a drop of only around 5% throughput when compared to a full crossbar, for a non-permutation i.e. contentious routing)
"matrix form".... outputs on the left as rows, inputs at the top as columns. every cell in the matrix has a T-Gate. a unary encoder per column sets mutually-exclusively one AND ONLY row-to-column T-Gate.
requires only NxN T-Gates plus N N-bit unary encoders.
which is a hell of a lot less gates than a full butterfly and a HELL of a hell of a lot less gates than a full N-to-N crossbar.
Also T gates make for significantly reduced logic cells although voltage is lost at each stage, buffers fix that. https://en.m.wikipedia.org/wiki/Transmission_gate
Quite a few nonstandard digital cell designs exist and can be used to simplify a circuit, but definitely not the design process, because you need to know when to use them and when not to use them.
... and most proprietary toolchains avoid them for precisely that reason. except... we're not *using* proprietary toolchains... :)
l.
Hello Luk, Hello List.
On 1/3/19 1:40 AM, Luke Kenneth Casson Leighton wrote:
Can I make a special request to include a T gate (transmission gate) in that list as it is a critical and little understood component of an efficient NxN crossbar.
Well, transmission gates are already on the list. Or being more earnest - they are the point where my Standard Cell Library stuck. Most effective (in meaning of size and transistor count) cells with storage (Latches) and multiplexer are based on transmission gates.
I really like to measure both transistors first, as components, before I compose transfer gates out of them. So they don't get it to the PearlRiver.
But yes, transfer gates are feasible, on the wish list and you'll get them as soon as the PMOS and NMOS are characterized with PearlRiver :-)
And regarding your NxN crossbar - for a quite nice RISC-V multiplier I already planed to hand-crafting a Barrel Shifter (https://en.wikipedia.org/wiki/Barrel_shifter) which is a structure close to your crossbar.
Thanks for reminding me!
Regards, Hagen.
Hi all,
On Thu, Jan 3, 2019 at 8:43 AM Hagen SANKOWSKI hsank@posteo.de wrote:
Well, transmission gates are already on the list. Or being more earnest
- they are the point where my Standard Cell Library stuck. Most
effective (in meaning of size and transistor count) cells with storage (Latches) and multiplexer are based on transmission gates.
I really like to measure both transistors first, as components, before I compose transfer gates out of them. So they don't get it to the PearlRiver.
For static measurements, this is the way to go. For high speed and precision measurements, where parasitic capacitances play a role, dedicated transmission gate test structures make sense - as a second step.
But yes, transfer gates are feasible, on the wish list and you'll get them as soon as the PMOS and NMOS are characterized with PearlRiver :-)
Isolated bulk and high voltage switches for charge pumps etc. are also insteresting ... as later step.
And regarding your NxN crossbar - for a quite nice RISC-V multiplier I already planed to hand-crafting a Barrel Shifter (https://en.wikipedia.org/wiki/Barrel_shifter) which is a structure close to your crossbar.
As essentially analog guy, I tend to want to focus on basic building blocks first.
Christoph
Hello Christoph! Hello List.
On 1/3/19 9:04 AM, Christoph Maier wrote:
But yes, transfer gates are feasible, on the wish list and you'll get them as soon as the PMOS and NMOS are characterized with PearlRiver :-)
Isolated bulk and high voltage switches for charge pumps etc. are also insteresting ... as later step.
You can see what we already have for PearlRiver here: https://github.com/chipforge/PearlRiver/tree/master/Library/magic
In this Library Directory are
high voltage Mosfets - L500_HVNFET_W108_L22_params.mag - L500_HVPFET_W108_L22_params.mag
isolated Mosfets, Ferec voted for - L500_NMOSi_W10_L10_params.mag - L500_NMOSi_W20_L20_params.mag - L500_NMOSi_W3_L2_params.mag - L500_NMOSi_W3_L3_params.mag - L500_NMOSi_W3_L8_params.mag - L500_NMOSi_W40_L40_params.mag - L500_NMOSi_W5_L5_params.mag - L500_NMOSi_W8_L3_params.mag - L500_NMOSi_W8_L8_params.mag
BJT - L500_NPN1.mag - L500_NPN2.mag - L500_PNP1.mag - L500_PNP2.mag
isolated NPN BJT - L500_NPNi1.mag - L500_NPNi2.mag
BTW, all sizes are in Lambda (as half the feature size Lambda is 500nm), hence the L500 in the file names.
Let's play :-)
Hi, Hagen,
please provide me with the literature for the PLL, I can try to design it, as I learned electrical engineering last century :-) Maybe, I am successful.
Cheers,
Ludwig
On Thu, Jan 3, 2019 at 9:27 AM Hagen SANKOWSKI hsank@posteo.de wrote:
Hello Christoph! Hello List.
On 1/3/19 9:04 AM, Christoph Maier wrote:
But yes, transfer gates are feasible, on the wish list and you'll get them as soon as the PMOS and NMOS are characterized with PearlRiver :-)
Isolated bulk and high voltage switches for charge pumps etc. are also insteresting ... as later step.
You can see what we already have for PearlRiver here: https://github.com/chipforge/PearlRiver/tree/master/Library/magic
In this Library Directory are
high voltage Mosfets
- L500_HVNFET_W108_L22_params.mag
- L500_HVPFET_W108_L22_params.mag
isolated Mosfets, Ferec voted for
- L500_NMOSi_W10_L10_params.mag
- L500_NMOSi_W20_L20_params.mag
- L500_NMOSi_W3_L2_params.mag
- L500_NMOSi_W3_L3_params.mag
- L500_NMOSi_W3_L8_params.mag
- L500_NMOSi_W40_L40_params.mag
- L500_NMOSi_W5_L5_params.mag
- L500_NMOSi_W8_L3_params.mag
- L500_NMOSi_W8_L8_params.mag
BJT
- L500_NPN1.mag
- L500_NPN2.mag
- L500_PNP1.mag
- L500_PNP2.mag
isolated NPN BJT
- L500_NPNi1.mag
- L500_NPNi2.mag
BTW, all sizes are in Lambda (as half the feature size Lambda is 500nm), hence the L500 in the file names.
Let's play :-) _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
On Thu, Jan 3, 2019, 13:49 Hagen SANKOWSKI <hsank@posteo.de wrote:
On 1/3/19 10:39 AM, ludwig jaffe wrote:
please provide me with the literature for the PLL, I can try to design it, as I learned electrical engineering last century :-) Maybe, I am successful.
Okay. You'll get a PM as soon as I am back in my office :-)
Hold me on the running how it goes.
tatzelbrumm
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
On 1/3/19 3:31 PM, Christoph Maier wrote:
On 1/3/19 10:39 AM, ludwig jaffe wrote: > please provide me with the literature for the PLL, I can try to design > it, as I learned electrical engineering last century :-) > Maybe, I am successful. Okay. You'll get a PM as soon as I am back in my office :-)Hold me on the running how it goes.
Okay. As long as I do not spread my material public which could be copyrighted by others.
On Thu, Jan 3, 2019, 15:34 Hagen SANKOWSKI <hsank@posteo.de wrote:
On 1/3/19 3:31 PM, Christoph Maier wrote:
On 1/3/19 10:39 AM, ludwig jaffe wrote: > please provide me with the literature for the PLL, I can try todesign
> it, as I learned electrical engineering last century :-) > Maybe, I am successful. Okay. You'll get a PM as soon as I am back in my office :-)Hold me on the running how it goes.
Okay. As long as I do not spread my material public which could be copyrighted by others.
Which leads to the question what we need to do to prior-art our stuff immediately.
On 1/3/19 3:41 PM, Christoph Maier wrote:
Which leads to the question what we need to do to prior-art our stuff immediately.
Publishing a Donald Duck Story about the topic:
https://www.iusmentis.com/patents/priorart/donaldduck :-)
Or, more seriously, publishing the stuff we have at github (or other repositories) 'cause of the timestamp on every check-in.
Using not so common repositories doesn't help, because you would have to show that the repository was already online before the patented stuff.
So I recommend, that both of you, Ludwig and Christoph getting your own (fresh new) identity on github.com and connecting this repositories with ours. Better way to keep this divided from former/personal identities on github.
Regards, Hagen.
Hello Everyone,
Congratulations for the 35C3 presentation. I could not be there personally, but I checked it out online. For the ADC topic, I would suggest to start with a 10 to 12 bit SAR, built around a R-2R or divide-add DAC at first. The SAR is fairly common in general-purpose MCUs, and these architectures are both need no special features (pure MOS design) and can be designed relatively easily (both DACs are a series of identical cells, allowing for a bottom-up design).
Regards, Ferenc
On Wed, Jan 2, 2019 at 2:30 PM Christoph Maier < cm.hardware.software.elsewhere@gmail.com> wrote:
Hi Tim,
On Wed, Jan 2, 2019 at 2:15 PM Tim Edwards tim@opencircuitdesign.com wrote:
Hello Christoph a.k.a. Tatzelbrumm:
Setting up lines of communication <mumble mumble> and refreshing memories <Hasler [Pronouns: she, her], Diorio, Minch>(remember those, Mr. Potbox?) <SONOS> in order to get involved and productive.
I have not been in contact with Jen Hasler since the early 2000s, but I have been in touch with one of her associates previously at Georgia Tech, Brian "Degs" Degnan, who was involved in the first customer taped-out design from efabless (currently in fab). Chris Diorio, I have not heard from since the late 1990s. Brad Minch still occasionally exchanges emails with me about various EDA tool issues.
I was just thinking about some non-standard analog structures one might try out on the Pearl River process (speaking of, I had some AFGAs on AMS CXE or some such and tested/fried them when visiting newly established assistant professor PAUL Hasler at Georgia Tech in 2000).
If it's possible to design an ADC in the Libre-Silicon process, then maybe it's time to start discussing onboarding the process on the efabless design platform.
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
TTYL soon Christoph
---Tim+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
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Hi All,
A SAR would be interesting, especially if you add a multiplexer for the clock! So clock should be selectable between programmable frequency divider from internal clock and also to be set to external clock. External clock is important if one has noise generated by switch mode power supply or just AC (50Hz/60Hz). External clock allows to synchronize the sampling clock with the noise and thus helps to eliminate the noise from the samples because of the averaging effect of SAR. May be we are able to have a PLL with a programmable frequency divider to generate higher Sampling frequencies that can be synchronized with external clock. If not, we would require an external PLL.
Cheers,
Ludwig
On Thu, Jan 3, 2019 at 1:22 AM Éger Ferenc eegerferenc@gmail.com wrote:
Hello Everyone,
Congratulations for the 35C3 presentation. I could not be there personally, but I checked it out online. For the ADC topic, I would suggest to start with a 10 to 12 bit SAR, built around a R-2R or divide-add DAC at first. The SAR is fairly common in general-purpose MCUs, and these architectures are both need no special features (pure MOS design) and can be designed relatively easily (both DACs are a series of identical cells, allowing for a bottom-up design).
Regards, Ferenc
On Wed, Jan 2, 2019 at 2:30 PM Christoph Maier < cm.hardware.software.elsewhere@gmail.com> wrote:
Hi Tim,
On Wed, Jan 2, 2019 at 2:15 PM Tim Edwards tim@opencircuitdesign.com wrote:
Hello Christoph a.k.a. Tatzelbrumm:
Setting up lines of communication <mumble mumble> and refreshing memories <Hasler [Pronouns: she, her], Diorio, Minch>(remember those, Mr. Potbox?) <SONOS> in order to get involved and productive.
I have not been in contact with Jen Hasler since the early 2000s, but I have been in touch with one of her associates previously at Georgia Tech, Brian "Degs" Degnan, who was involved in the first customer taped-out design from efabless (currently in fab). Chris Diorio, I have not heard from since the late 1990s. Brad Minch still occasionally exchanges emails with me about various EDA tool issues.
I was just thinking about some non-standard analog structures one might try out on the Pearl River process (speaking of, I had some AFGAs on AMS CXE or some such and tested/fried them when visiting newly established assistant professor PAUL Hasler at Georgia Tech in 2000).
If it's possible to design an ADC in the Libre-Silicon process, then maybe it's time to start discussing onboarding the process on the efabless design platform.
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
TTYL soon Christoph
---Tim+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com
|
| Open Circuit Design | web: http://opencircuitdesign.com
|
| 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hello Ludwig, Hello List.
On 1/3/19 7:45 AM, ludwig jaffe wrote:
A SAR would be interesting, especially if you add a multiplexer for the clock!
There is a clock-gate on the list for the Standard Cell Library already, which contains also the Latch behind the multiplexer (https://en.wikipedia.org/wiki/Clock_gating). Wikipedia miss the Latch btw :-o
May be we are able to have a PLL with a programmable frequency divider to generate higher Sampling frequencies that can be synchronized with external clock. If not, we would require an external PLL.
Well, Phase-locked Loops are very hard to design. IMHO the complexity is similar to ADCs. On the PearlRiver we already have 3 types of ring-oscillators, which are not stable enough while changing frequency with PVT (process-voltage-temperature) parameters. Here we use this effect to measure PVT influence..
Please feel free to design a PLL also. As soon as the technology nodes going down, and the internal feasible clock frequency rises over the cut-off frequency of any IO-Cells we are need them! Because we can not feed the internal clock from external anymore without a PLL.
I can provide everybody, who likes to design our first PLL, with a bunch of literature. But this guy should be an Analog one, not me as a Digital.
Regards, Hagen.
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David Lanzendörfer -
Hagen SANKOWSKI -
ludwig jaffe -
Luke Kenneth Casson Leighton -
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Éger Ferenc