Hi folks Going through the process over and over again I have to appreciate Stafs input on the gate alignment. Already with 1um it's very difficult to get a proper alignment of the overlap of the drain/source and the gate. Maybe we should consider poly silicon after all? (It won't affect the layout)
Cheers David
How do you want to handle that later with smaller nodes? I think they all have the problem of aligning gates, isn't it?
On 03/06/2018 10:33 AM, David Lanzendörfer wrote:
Hi folks Going through the process over and over again I have to appreciate Stafs input on the gate alignment. Already with 1um it's very difficult to get a proper alignment of the overlap of the drain/source and the gate. Maybe we should consider poly silicon after all? (It won't affect the layout)
Cheers David
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hi
How do you want to handle that later with smaller nodes?
For that it would be interesting to have access to the full IEEE document here: http://ieeexplore.ieee.org/document/5984621 They apparently made it work.
I think they all have the problem of aligning gates, isn't it?
This document thematizes that very well. http://electroiq.com/blog/2010/03/integrating-high-k
Gate-first-gate-last problem, is exactly what we have here right now. If we use poly for the gate first we will have a problem with grainyness but if we do gate-last with Aluminum we will have a alignement issue.
The attached picture delivers us an idea for gate-last self-aligning
Cheers David
Hi
How do you want to handle that later with smaller nodes?
For that it would be interesting to have access to the full IEEE document here: http://ieeexplore.ieee.org/document/5984621 They apparently made it work.
I think they all have the problem of aligning gates, isn't it?
This document thematizes that very well. http://electroiq.com/blog/2010/03/integrating-high-k
Gate-first-gate-last problem, is exactly what we have here right now. If we use poly for the gate first we will have a problem with grainyness but if we do gate-last with Aluminum we will have a alignement issue.
Or that method for Aluminum: http://km2000.us/franklinduan/articles/images/high_k88.jpg
We can use a dummy gate and then use the damazene method to add the actual Aluminum gate electrode. I'm actually eager to go for this, because poly silicon is very grainy as I've explained to George today over some beers. It will be a problem to have exact geometric structures with 28nm when using poly for the gate electrode. Also we loose the "4.1 volt advantage" when it comes to threshold drops. (E_Al = V_M*q = 4.1 eV -> V_M = 4.1V)
Cheers David
Hi In the book "ULSI Process Integration 5" I've found some detailed description of the usage of dummy-gates for gate-last manufacturing.
https://books.google.com.hk/books? id=o3zXAiskEYUC&lpg=PA319&ots=sD2_WDEV6A&dq=gate-last%20cmos%20dummy- gate&pg=PA319#v=onepage&q=gate-last%20cmos%20dummy-gate&f=false
There are also pros and cons listed for gate-last vs. gate-first
What do you folks think? What's the smarter choice?
Cheers
On Tuesday, 6 March 2018 10:14:05 PM HKT David Lanzendörfer wrote:
Hi
How do you want to handle that later with smaller nodes?
For that it would be interesting to have access to the full IEEE document here: http://ieeexplore.ieee.org/document/5984621 They apparently made it work.
I think they all have the problem of aligning gates, isn't it?
This document thematizes that very well. http://electroiq.com/blog/2010/03/integrating-high-k
Gate-first-gate-last problem, is exactly what we have here right now. If we use poly for the gate first we will have a problem with grainyness but if we do gate-last with Aluminum we will have a alignement issue.
Or that method for Aluminum: http://km2000.us/franklinduan/articles/images/high_k88.jpg
We can use a dummy gate and then use the damazene method to add the actual Aluminum gate electrode. I'm actually eager to go for this, because poly silicon is very grainy as I've explained to George today over some beers. It will be a problem to have exact geometric structures with 28nm when using poly for the gate electrode. Also we loose the "4.1 volt advantage" when it comes to threshold drops. (E_Al = V_M*q = 4.1 eV -> V_M = 4.1V)
Cheers David
David, Could you summarize again what the problem is with poly gate?In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm. greets,Staf. David Lanzendörfer schreef op wo 07-03-2018 om 04:55 [+0800]:
Hi In the book "ULSI Process Integration 5" I've found some detailed description of the usage of dummy-gates for gate-last manufacturing.
https://books.google.com.hk/books? id=o3zXAiskEYUC&lpg=PA319&ots=sD2_WDEV6A&dq=gate-last%20cmos%20dummy- gate&pg=PA319#v=onepage&q=gate-last%20cmos%20dummy-gate&f=false
There are also pros and cons listed for gate-last vs. gate-first
What do you folks think? What's the smarter choice?
Cheers
On Tuesday, 6 March 2018 10:14:05 PM HKT David Lanzendörfer wrote:
Hi
How do you want to handle that later with smaller nodes?
For that it would be interesting to have access to the full IEEE document here: http://ieeexplore.ieee.org/document/5984621 They apparently made it work.
I think they all have the problem of aligning gates, isn't it?
This document thematizes that very well. http://electroiq.com/blog/2010/03/integrating-high-k
Gate-first-gate-last problem, is exactly what we have here right now. If we use poly for the gate first we will have a problem with grainyness but if we do gate-last with Aluminum we will have a alignement issue.
Or that method for Aluminum: http://km2000.us/franklinduan/articles/images/high_k88.jpg
We can use a dummy gate and then use the damazene method to add the actual Aluminum gate electrode. I'm actually eager to go for this, because poly silicon is very grainy as I've explained to George today over some beers. It will be a problem to have exact geometric structures with 28nm when using poly for the gate electrode. Also we loose the "4.1 volt advantage" when it comes to threshold drops. (E_Al = V_M*q = 4.1 eV -> V_M = 4.1V)
Cheers David
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hello Staf,
Could you summarize again what the problem is with poly gate? In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm.
What is commonly drawn as a poly gate is actually a "salicide", or poly coated with a thin layer of metal. This is what David is referring to. The difference between a poly salicide and plain polysilicon is a few ohms per square vs. a hundred ohms per square.
---Tim
+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
(Now send to the list.) R. Timothy Edwards schreef op di 06-03-2018 om 16:48 [-0500]:
Hello Staf,
Could you summarize again what the problem is with poly gate? In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm.
What is commonly drawn as a poly gate is actually a "salicide", or poly coated with a thin layer of metal. This is what David is referring to. The difference between a poly salicide and plain polysilicon is a few ohms per square vs. a hundred ohms per square.
AFAIK, David is talking about aluminum gates. Silicidation or salidication is indeed a step done after poly formation to decrease sheet resistance of the poly. AFAIR also the diffusion regions are silicided but I think you need spacers then.
greets, Staf.
Hi What I'm taling about in indeed a mix between our metal and polysilicon as described here in these lecture slides: https://web.stanford.edu/class/ee311/NOTES/Silicides%20&%20Metal%20gate %20Slides.pdf
This polycrystal resulting from this process step would be resistant against the temperatures during annealing after implantation.
However. Getting the reaction of Aluminum and Polysilicon right will be very very tricky.
Anyone experience with this step, or knows someone who does, who could assist me with setting the parameters for time and temperature and atmosphere?
Otherwise I would have to experiment around a few times until I get it right with orientation numbers I find with Googling ^^'
Cheers David
On Wednesday, 7 March 2018 5:04:05 PM HKT Staf Verhaegen wrote:
(Now send to the list.)
R. Timothy Edwards schreef op di 06-03-2018 om 16:48 [-0500]:
Hello Staf,
Could you summarize again what the problem is with poly gate? In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm.
What is commonly drawn as a poly gate is actually a "salicide", or poly coated with a thin layer of metal. This is what David is referring to. The difference between a poly salicide and plain polysilicon is a few ohms per square vs. a hundred ohms per square.
AFAIK, David is talking about aluminum gates. Silicidation or salidication is indeed a step done after poly formation to decrease sheet resistance of the poly. AFAIR also the diffusion regions are silicided but I think you need spacers then.
greets, Staf.
Hi These rapid thermal process machines AW610 RTP (DIF-R2) and AW610 RTP (DIF-R3) can both deposite silicides: http://www.nff.ust.hk/en/equipment-and-process/equipment-list/thermal-diffus...
I will check which materials are available. -> "Is it WSi2 or AlSi2?" plays into the threshold equation!
I'll keep you updated!
Cheers David
On Wednesday, 7 March 2018 6:45:15 PM HKT David Lanzendörfer wrote:
Hi What I'm taling about in indeed a mix between our metal and polysilicon as described here in these lecture slides: https://web.stanford.edu/class/ee311/NOTES/Silicides%20&%20Metal%20gate %20Slides.pdf
This polycrystal resulting from this process step would be resistant against the temperatures during annealing after implantation.
However. Getting the reaction of Aluminum and Polysilicon right will be very very tricky.
Anyone experience with this step, or knows someone who does, who could assist me with setting the parameters for time and temperature and atmosphere?
Otherwise I would have to experiment around a few times until I get it right with orientation numbers I find with Googling ^^'
Cheers David
On Wednesday, 7 March 2018 5:04:05 PM HKT Staf Verhaegen wrote:
(Now send to the list.)
R. Timothy Edwards schreef op di 06-03-2018 om 16:48 [-0500]:
Hello Staf,
Could you summarize again what the problem is with poly gate? In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm.
What is commonly drawn as a poly gate is actually a "salicide", or poly coated with a thin layer of metal. This is what David is referring to. The difference between a poly salicide and plain polysilicon is a few ohms per square vs. a hundred ohms per square.
AFAIK, David is talking about aluminum gates. Silicidation or salidication is indeed a step done after poly formation to decrease sheet resistance of the poly. AFAIR also the diffusion regions are silicided but I think you need spacers then.
greets, Staf.
Figured it out... Doesn't depend on the machine, but on what elementary metal we deposit on top of the silicon... Ok. I think I change the process to gate-first with silicides and go through the pain of dimensioning the temperature and time for the silicide formation... Aaand updating the equations for the threshold calculation for accounting for the changed gate potential....
Cheers David
On Wednesday, 7 March 2018 7:22:08 PM HKT David Lanzendörfer wrote:
Hi These rapid thermal process machines AW610 RTP (DIF-R2) and AW610 RTP (DIF-R3) can both deposite silicides: http://www.nff.ust.hk/en/equipment-and-process/equipment-list/thermal-diffu sion-and-ion-implantation-module.html
I will check which materials are available. -> "Is it WSi2 or AlSi2?" plays into the threshold equation!
I'll keep you updated!
Cheers David
On Wednesday, 7 March 2018 6:45:15 PM HKT David Lanzendörfer wrote:
Hi What I'm taling about in indeed a mix between our metal and polysilicon as described here in these lecture slides: https://web.stanford.edu/class/ee311/NOTES/Silicides%20&%20Metal%20gate %20Slides.pdf
This polycrystal resulting from this process step would be resistant against the temperatures during annealing after implantation.
However. Getting the reaction of Aluminum and Polysilicon right will be very very tricky.
Anyone experience with this step, or knows someone who does, who could assist me with setting the parameters for time and temperature and atmosphere?
Otherwise I would have to experiment around a few times until I get it right with orientation numbers I find with Googling ^^'
Cheers
David
On Wednesday, 7 March 2018 5:04:05 PM HKT Staf Verhaegen wrote:
(Now send to the list.)
R. Timothy Edwards schreef op di 06-03-2018 om 16:48 [-0500]:
Hello Staf,
Could you summarize again what the problem is with poly gate? In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm.
What is commonly drawn as a poly gate is actually a "salicide", or poly coated with a thin layer of metal. This is what David is referring to. The difference between a poly salicide and plain polysilicon is a few ohms per square vs. a hundred ohms per square.
AFAIK, David is talking about aluminum gates. Silicidation or salidication is indeed a step done after poly formation to decrease sheet resistance of the poly. AFAIR also the diffusion regions are silicided but I think you need spacers then.
greets, Staf.
Hi This patent contains some hints on how to build our polysilicon gates with low resistance: -> https://patents.google.com/patent/US6387788
It's as Tim said, there is usually a film of conducting metal added onto the polysilicon and then heated to reacht with the polisilicon and form a conducting ceramic: -> https://en.wikipedia.org/wiki/Tungsten_disilicide -> https://en.wikipedia.org/wiki/Titanium_disilicide
Just that we have to turn the thin metal layer, which we deposit into a conducting ceramic in order to make it resist the temperatures during further processing and the unreacted metal needs to be removed: -> https://patents.google.com/patent/DE69931068T2
The sputterer at HKUST can do Titanium -> http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-etching-an...
And we can grow polysilicon: -> http://www.nff.ust.hk/en/equipment-and-process/equipment-list/thermal-diffus...
But I think we can first just use polysilicon. At least it conducts, even when the resistance is very high, and then in the next step we can start tinkering around with reducing the resistance of the gate electrode.
What do you think?
Cheers David
On Wednesday, 7 March 2018 7:25:42 PM HKT David Lanzendörfer wrote:
Figured it out... Doesn't depend on the machine, but on what elementary metal we deposit on top of the silicon... Ok. I think I change the process to gate-first with silicides and go through the pain of dimensioning the temperature and time for the silicide formation... Aaand updating the equations for the threshold calculation for accounting for the changed gate potential....
Cheers David
On Wednesday, 7 March 2018 7:22:08 PM HKT David Lanzendörfer wrote:
Hi These rapid thermal process machines AW610 RTP (DIF-R2) and AW610 RTP (DIF-R3) can both deposite silicides: http://www.nff.ust.hk/en/equipment-and-process/equipment-list/thermal-diff u sion-and-ion-implantation-module.html
I will check which materials are available. -> "Is it WSi2 or AlSi2?" plays into the threshold equation!
I'll keep you updated!
Cheers
David
On Wednesday, 7 March 2018 6:45:15 PM HKT David Lanzendörfer wrote:
Hi What I'm taling about in indeed a mix between our metal and polysilicon as described here in these lecture slides: https://web.stanford.edu/class/ee311/NOTES/Silicides%20&%20Metal%20gate %20Slides.pdf
This polycrystal resulting from this process step would be resistant against the temperatures during annealing after implantation.
However. Getting the reaction of Aluminum and Polysilicon right will be very very tricky.
Anyone experience with this step, or knows someone who does, who could assist me with setting the parameters for time and temperature and atmosphere?
Otherwise I would have to experiment around a few times until I get it right with orientation numbers I find with Googling ^^'
Cheers
David
On Wednesday, 7 March 2018 5:04:05 PM HKT Staf Verhaegen wrote:
(Now send to the list.)
R. Timothy Edwards schreef op di 06-03-2018 om 16:48 [-0500]:
Hello Staf,
Could you summarize again what the problem is with poly gate? In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm.
What is commonly drawn as a poly gate is actually a "salicide", or poly coated with a thin layer of metal. This is what David is referring to. The difference between a poly salicide and plain polysilicon is a few ohms per square vs. a hundred ohms per square.
AFAIK, David is talking about aluminum gates. Silicidation or salidication is indeed a step done after poly formation to decrease sheet resistance of the poly. AFAIR also the diffusion regions are silicided but I think you need spacers then.
greets, Staf.
Wow, we dig deeper in technology stuff, as I assumed..
On 03/07/2018 02:47 PM, David Lanzendörfer wrote:
This patent contains some hints on how to build our polysilicon gates with low resistance: -> https://patents.google.com/patent/US6387788
Well, google also said the patent is "Expired - Fee Related". Means, we can use it, right?
BTW, avoiding patents always means "know your enemy".
@David, can you please provide somewhere in the wiki a list of patents we are aware (and avoiding)? Just to document we know them and keep them out of the way.
Hi
Wow, we dig deeper in technology stuff, as I assumed..
Of course! We're developing our own process! ;-) So what do you think? Should we just use a polysilicon strip for now, in order to make sure that our gate is aligned? As soon as we scale down, we can still throw some Titanium at it during as a shoved in process substep, bake it in and make Titanium-polycid for reducing the resistance.
On 03/07/2018 02:47 PM, David Lanzendörfer wrote:
This patent contains some hints on how to build our polysilicon gates with low resistance: -> https://patents.google.com/patent/US6387788
Well, google also said the patent is "Expired - Fee Related". Means, we can use it, right?
I guess so... Cedric is also here on the mailinglist, he's our legal protector (among many other very important taks), and he already has given me the task to collect a list of all the patents we're touching, so that he can make sure, that we're on the safe side from a legal perspective.
BTW, avoiding patents always means "know your enemy".
Well. Better we know that we do something like someone else. It's wise to google your approach before you start manufacuting products in a certain way and try to sell them. Because even if you didn't know that the method has been patented, it is and the patent holder might sue the shit out of us. So it's better to check whether the patent is still on, and if yes, choose another approach :-)
@David, can you please provide somewhere in the wiki a list of patents we are aware (and avoiding)? Just to document we know them and keep them out of the way.
I will extract all the footnotes from the LaTeX document and filter them for patents, yeah :-)
Cheers David
Hi
Wow, we dig deeper in technology stuff, as I assumed..
I think, we just use polysilicon for now, as described here on page 27: https://books.google.com.hk/books?id=1Z3zBwAAQBAJ&lpg=PP1&pg=PP1#v=o... Makes sure we have gate-aligning in the future...
Cheers David
On 03/07/2018 02:47 PM, David Lanzendörfer wrote:
This patent contains some hints on how to build our polysilicon gates with low resistance: -> https://patents.google.com/patent/US6387788
Well, google also said the patent is "Expired - Fee Related". Means, we can use it, right?
BTW, avoiding patents always means "know your enemy".
@David, can you please provide somewhere in the wiki a list of patents we are aware (and avoiding)? Just to document we know them and keep them out of the way.
David Lanzendörfer schreef op wo 07-03-2018 om 18:45 [+0800]:
Hi
Otherwise I would have to experiment around a few times until I get it right with orientation numbers I find with Googling ^^'
David, I want to be blunt; if you are not prepared to do this for most of the steps in the process it's time to stop the project now. As I said already during the phone I consider what you guys are currently doing is preparation to start the process development. For the litho steps you will also need to determine best dose and focus, check if alignment works. For dry etching steps you will need to determine the end point detection, etc. Let me compare it to some guys who have read some paper on operating system development, have now made a schematic layout of how the OS will look and now in the process of planning to start to write the first code...
greets, Staf.
Yes. I'm aware of this. It's just a lot of "power" we have here, in the sense that we have to make so many decisions on materials and so on. Please give your take on the material choice. Yes. We're in the preparation phase and then we test it. We. Know. What we need is some experience values. Some answers to simple questions like: -> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"? -> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
And stopping is certainly *not* an option.
Cheers David
On Wednesday, 7 March 2018 10:38:43 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 18:45 [+0800]:
Hi
Otherwise I would have to experiment around a few times until I get it right with orientation numbers I find with Googling ^^'
David, I want to be blunt; if you are not prepared to do this for most of the steps in the process it's time to stop the project now. As I said already during the phone I consider what you guys are currently doing is preparation to start the process development. For the litho steps you will also need to determine best dose and focus, check if alignment works. For dry etching steps you will need to determine the end point detection, etc. Let me compare it to some guys who have read some paper on operating system development, have now made a schematic layout of how the OS will look and now in the process of planning to start to write the first code...
greets, Staf.
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]:
-> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide ? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
-> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
Hi
But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-etching-an... 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]:
-> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
-> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
Hi I've found this article, describing how to form the titanium silicide: http://ic-garden.cn/?p=829
I think I will adapt this into our process.
Cheers David
On Thursday, 8 March 2018 4:19:31 PM HKT David Lanzendörfer wrote:
Hi
But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-etching-a nd-sputtering-module.html 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]:
-> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
-> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
I've decided to add titanium silicide, because the drain/source regions are pretty shallow and without the titanium silicide as depth controller we might etch too far and miss the drain/source.
Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
On Thursday, 8 March 2018 9:21:53 PM HKT David Lanzendörfer wrote:
Hi I've found this article, describing how to form the titanium silicide: http://ic-garden.cn/?p=829
I think I will adapt this into our process.
Cheers David
On Thursday, 8 March 2018 4:19:31 PM HKT David Lanzendörfer wrote:
Hi
But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-etching -a nd-sputtering-module.html 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers
David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]:
-> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
-> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
For everyone who can't read Chinese on this list (;-)) : This is the manual from IBM for how to build silicide structures: https://pan.baidu.com/s/1c0AtLNq
I will orient myself on this for siliciding the gate and the drain/source area.
Cheers David
On Thursday, 8 March 2018 9:24:03 PM HKT David Lanzendörfer wrote:
I've decided to add titanium silicide, because the drain/source regions are pretty shallow and without the titanium silicide as depth controller we might etch too far and miss the drain/source.
Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
On Thursday, 8 March 2018 9:21:53 PM HKT David Lanzendörfer wrote:
Hi I've found this article, describing how to form the titanium silicide: http://ic-garden.cn/?p=829
I think I will adapt this into our process.
Cheers
David
On Thursday, 8 March 2018 4:19:31 PM HKT David Lanzendörfer wrote:
Hi
But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-etchin g -a nd-sputtering-module.html 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers
David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]:
-> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
-> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
And Staf: Yes. We need spacers when forming silicid/policid, or we would get a short between the gate and the drain and source. I'm working on the steps of how to build the poly-gate and push the changes as soon as I'm done. You can have a look at the *initial* version of alignment strategy chapter. Feel free to add content at your discretion ;-)
Cheers David
On Thursday, 8 March 2018 9:35:01 PM HKT David Lanzendörfer wrote:
For everyone who can't read Chinese on this list (;-)) : This is the manual from IBM for how to build silicide structures: https://pan.baidu.com/s/1c0AtLNq
I will orient myself on this for siliciding the gate and the drain/source area.
Cheers David
On Thursday, 8 March 2018 9:24:03 PM HKT David Lanzendörfer wrote:
I've decided to add titanium silicide, because the drain/source regions are pretty shallow and without the titanium silicide as depth controller we might etch too far and miss the drain/source.
Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
On Thursday, 8 March 2018 9:21:53 PM HKT David Lanzendörfer wrote:
Hi I've found this article, describing how to form the titanium silicide: http://ic-garden.cn/?p=829
I think I will adapt this into our process.
Cheers
David
On Thursday, 8 March 2018 4:19:31 PM HKT David Lanzendörfer wrote:
Hi
But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-etch in g -a nd-sputtering-module.html 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers
David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]:
-> Do we need to fight with silicides from the beginning or can we just start with polysilicon in order to get something "kindof working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
-> Do you know someone who has experience with the step of producing silicides and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
We will need another mask for forming the spacers, and the oxide layer is thick enough, so that there is no silicid touching the gate-poly with 1um. I suggest we go without spacer so far (did some study on spacers and their function now)
But the silicid is certainly helpful for depth control during etching.
Cheers David
On Thursday, 8 March 2018 10:02:04 PM HKT David Lanzendörfer wrote:
And Staf: Yes. We need spacers when forming silicid/policid, or we would get a short between the gate and the drain and source. I'm working on the steps of how to build the poly-gate and push the changes as soon as I'm done. You can have a look at the *initial* version of alignment strategy chapter. Feel free to add content at your discretion ;-)
Cheers David
On Thursday, 8 March 2018 9:35:01 PM HKT David Lanzendörfer wrote:
For everyone who can't read Chinese on this list (;-)) : This is the manual from IBM for how to build silicide structures: https://pan.baidu.com/s/1c0AtLNq
I will orient myself on this for siliciding the gate and the drain/source area.
Cheers
David
On Thursday, 8 March 2018 9:24:03 PM HKT David Lanzendörfer wrote:
I've decided to add titanium silicide, because the drain/source regions are pretty shallow and without the titanium silicide as depth controller we might etch too far and miss the drain/source.
Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
On Thursday, 8 March 2018 9:21:53 PM HKT David Lanzendörfer wrote:
Hi I've found this article, describing how to form the titanium silicide: http://ic-garden.cn/?p=829
I think I will adapt this into our process.
Cheers
David
On Thursday, 8 March 2018 4:19:31 PM HKT David Lanzendörfer wrote:
Hi
But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-et ch in g -a nd-sputtering-module.html 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers
David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]: > -> Do we need to fight with silicides from the beginning or can > we > just start with polysilicon in order to get something "kindof > working"?
My expertise was in lithography so for me silicidation was a step done by other groups. So I don't know the details of the process. But I think the silicide was also used as stopping layer for the contact hole etch. Can you etch the contact holes without the silicide? Due to the big depth difference between the gate contacts and the source/drain contacts you need a good stopping layer otherwise you will just etch through the polysilicon.
> -> Do you know someone who has experience with the step of > producing > silicides > and polisilides for reducing the gate-resisitivity?
The environment was a classic work environment and I don't remember any open source sentiment from the time there. The people I knew there have either moved on in the management ladder or to other things. I think it is best to try to socialize with experts from the Hong Kong fab where you will do the processing.
greets, Staf.
Ok. I've digged further, and apparently there is a way to etch the spacers without an additional mask. It's called "anisotropic etching" and leaves behind online the oxide which has grown horizontally, ergo only the oxide covering the sidewalls of the polysilicon. I'm now ready to fill in the process steps into the gate-chapter. Stay tuned
Cheers David
On Thursday, 8 March 2018 11:21:56 PM HKT David Lanzendörfer wrote:
We will need another mask for forming the spacers, and the oxide layer is thick enough, so that there is no silicid touching the gate-poly with 1um. I suggest we go without spacer so far (did some study on spacers and their function now)
But the silicid is certainly helpful for depth control during etching.
Cheers David
On Thursday, 8 March 2018 10:02:04 PM HKT David Lanzendörfer wrote:
And Staf: Yes. We need spacers when forming silicid/policid, or we would get a short between the gate and the drain and source. I'm working on the steps of how to build the poly-gate and push the changes as soon as I'm done. You can have a look at the *initial* version of alignment strategy chapter. Feel free to add content at your discretion ;-)
Cheers
David
On Thursday, 8 March 2018 9:35:01 PM HKT David Lanzendörfer wrote:
For everyone who can't read Chinese on this list (;-)) : This is the manual from IBM for how to build silicide structures: https://pan.baidu.com/s/1c0AtLNq
I will orient myself on this for siliciding the gate and the drain/source area.
Cheers
David
On Thursday, 8 March 2018 9:24:03 PM HKT David Lanzendörfer wrote:
I've decided to add titanium silicide, because the drain/source regions are pretty shallow and without the titanium silicide as depth controller we might etch too far and miss the drain/source.
> Due to the big depth difference between the gate contacts and > the > source/drain contacts you need a good stopping layer otherwise > you > will > just etch through the polysilicon.
On Thursday, 8 March 2018 9:21:53 PM HKT David Lanzendörfer wrote:
Hi I've found this article, describing how to form the titanium silicide: http://ic-garden.cn/?p=829
I think I will adapt this into our process.
Cheers
David
On Thursday, 8 March 2018 4:19:31 PM HKT David Lanzendörfer wrote:
Hi
> But I think the silicide was also used as stopping layer for the > contact hole etch. Can you etch the contact holes without the > silicide? > Due to the big depth difference between the gate contacts and > the > source/drain contacts you need a good stopping layer otherwise > you > will > just etch through the polysilicon.
We can use BHF method, which selectively only etches oxide but nothing else. http://www.nff.ust.hk/en/equipment-and-process/equipment-list/dry-%3E > > > > > et ch in g -a nd-sputtering-module.html 6HF reacts with SiO2 into H2SiF6+H2O The polysilicon isn't oxidized, so there is no basis for a reaction, the oxygen atoms are missing.
With the "AOE Etcher (DRY-AOE)" from HKUST we can selectively etch the contact windows into the oxide, without putting too much stress at the polysilicon.
I guess this will work, but we will have to try it out.
Cheers
David
On Thursday, 8 March 2018 4:42:12 AM HKT Staf Verhaegen wrote: > David Lanzendörfer schreef op wo 07-03-2018 om 22:47 [+0800]: > > -> Do we need to fight with silicides from the beginning or > > can > > we > > just start with polysilicon in order to get something "kindof > > working"? > > My expertise was in lithography so for me silicidation was a > step > done > by other groups. So I don't know the details of the process. > But I think the silicide was also used as stopping layer for the > contact hole etch. Can you etch the contact holes without the > silicide? > Due to the big depth difference between the gate contacts and > the > source/drain contacts you need a good stopping layer otherwise > you > will > just etch through the polysilicon. > > > -> Do you know someone who has experience with the step of > > producing > > silicides > > and polisilides for reducing the gate-resisitivity? > > The environment was a classic work environment and I don't > remember > any > open source sentiment from the time there. The people I knew > there > have > either moved on in the management ladder or to other things. > I think it is best to try to socialize with experts from the > Hong > Kong > fab where you will do the processing. > > greets, > Staf.
Hi What I mean by this is the issue with graininess when you start doping the thing: http://www.iue.tuwien.ac.at/phd/puchner/node33.html Which will limit us in the sense that we can not reduce the ohmic resistance further and further. We will always be "worse in resistance" compared to an Aluminum gate. Also with Salicides we loos the advantage of the "builtin" +4.1V for the threshold voltages, we get from the Aluminum.
But the benefits in construction seem to outweight the ohmic disadvantages and the threshold issues, because the alignment problem will fall away.
What do you all think? Should we choose salicide structures like this one over Aluminum? https://www.silvaco.com/products/vwf/athena/ss4/ss4_fig18w.jpg
Or for the vote: gate-first or gate-last approach What do you vote for?
Cheers David
On Wednesday, 7 March 2018 5:07:35 AM HKT Staf Verhaegen wrote:
David, Could you summarize again what the problem is with poly gate?In the industry polysilicon has been the gate for all technologies I know from 1um up to at least 65nm. greets,Staf.
David Lanzendörfer schreef op wo 07-03-2018 om 04:55 [+0800]:
Hi In the book "ULSI Process Integration 5" I've found some detailed description of the usage of dummy-gates for gate-last manufacturing.
https://books.google.com.hk/books? id=o3zXAiskEYUC&lpg=PA319&ots=sD2_WDEV6A&dq=gate-last%20cmos%20dummy- gate&pg=PA319#v=onepage&q=gate-last%20cmos%20dummy-gate&f=false
There are also pros and cons listed for gate-last vs. gate-first
What do you folks think? What's the smarter choice?
Cheers
On Tuesday, 6 March 2018 10:14:05 PM HKT David Lanzendörfer wrote:
Hi
How do you want to handle that later with smaller nodes?
For that it would be interesting to have access to the full IEEE document here: http://ieeexplore.ieee.org/document/5984621 They apparently made it work.
I think they all have the problem of aligning gates, isn't it?
This document thematizes that very well. http://electroiq.com/blog/2010/03/integrating-high-k
Gate-first-gate-last problem, is exactly what we have here right now. If we use poly for the gate first we will have a problem with grainyness but if we do gate-last with Aluminum we will have a alignement issue.
Or that method for Aluminum: http://km2000.us/franklinduan/articles/images/high_k88.jpg
We can use a dummy gate and then use the damazene method to add the actual Aluminum gate electrode. I'm actually eager to go for this, because poly silicon is very grainy as I've explained to George today over some beers. It will be a problem to have exact geometric structures with 28nm when using poly for the gate electrode. Also we loose the "4.1 volt advantage" when it comes to threshold drops. (E_Al = V_M*q = 4.1 eV -> V_M = 4.1V)
Cheers
David
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
libresilicon-developers@list.libresilicon.com
-
David Lanzendörfer -
Hagen SANKOWSKI -
R. Timothy Edwards -
Staf Verhaegen