Hi all I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers.
Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers?
Cheers David
EDIT: Damn autocorrect... ^^' If you have a look into the document: I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers.
On Saturday, 10 March 2018 1:35:25 AM HKT David Lanzendörfer wrote:
Hi all I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers.
Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers?
Cheers David
David Lanzendörfer schreef op za 10-03-2018 om 01:35 [+0800]:
Can you folks think of any more test structures for the test-section besides
plain NMOS/PMOS and different caps and resistors using all the different layers?
A good exercise is to make the design rules chapter concrete with real values in them. For each of the rules determine what actually is the cause of this design rule (litho, etch, physics, ...) and then think about test structures to check if you meet the design rule in practice.
greets, Staf.
Hi Staf! Yes. Filling in the content in the "Design rules" chapter is clearly a task I'm planning to start working on that tomorrow! I intend to add some content to that chapter before the meeting on Sunday. Then we can discuss my results together. I hope we'll be hearing you in mumble on Sunday! ;-)
Cheers David
On Saturday, 10 March 2018 4:04:19 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op za 10-03-2018 om 01:35 [+0800]:
Can you folks think of any more test structures for the test-section besides
plain NMOS/PMOS and different caps and resistors using all the different layers?
A good exercise is to make the design rules chapter concrete with real values in them. For each of the rules determine what actually is the cause of this design rule (litho, etch, physics, ...) and then think about test structures to check if you meet the design rule in practice.
greets, Staf.
Hi Staf I've now started to add content to the design rule chapter. The lithography limits us to 0.5um or higher with its minimum line spacing. I'm now reworking the choice and parameters of all the machines and will add the design rules in iteratively over the next few days.
I'm working a lot on this, but a day has only so many hours and I also need to sleep and so :-)
I hope to hear from many people on this list on Sunday 9pm Hong Kong time!
Cheers David
On Saturday, 10 March 2018 4:04:19 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op za 10-03-2018 om 01:35 [+0800]:
Can you folks think of any more test structures for the test-section besides
plain NMOS/PMOS and different caps and resistors using all the different layers?
A good exercise is to make the design rules chapter concrete with real values in them. For each of the rules determine what actually is the cause of this design rule (litho, etch, physics, ...) and then think about test structures to check if you meet the design rule in practice.
greets, Staf.
Hello David,
I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers.
Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers?
I would think that you would want diodes, especially ESD structure diodes, and vertical bipolars to test latchup conditions, and maybe some lateral bipolars as well to see what the beta is.
And I agree with Staf that you will want to push the design rules, e.g., long metal, poly, and diffusion strips at close spacing to get a statistical distribution of how often they end up shorting.
Also long thin poly strips to get a statistical distribution of spot defects large enough to cause an open.
---Tim
+--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
Hi Tim! Would you please join us on Sundsay 9pm HKT? Because I think we first have to measure out the actual properties of what we are actuall building here, before we can do predictions on these details. But I'm eager to hear your take on that!
Cheers David
On Saturday, 10 March 2018 4:08:23 AM HKT Tim Edwards wrote:
Hello David,
I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers.
Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers?
I would think that you would want diodes, especially ESD structure diodes, and vertical bipolars to test latchup conditions, and maybe some lateral bipolars as well to see what the beta is.
And I agree with Staf that you will want to push the design rules, e.g., long metal, poly, and diffusion strips at close spacing to get a statistical distribution of how often they end up shorting.
Also long thin poly strips to get a statistical distribution of spot defects large enough to cause an open.
---Tim+--------------------------------+-------------------------------------+
| R. Timothy Edwards (Tim) | email: tim@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 |
+--------------------------------+-------------------------------------+ _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hi Tim
I would think that you would want diodes, especially ESD structure diodes, and vertical bipolars to test latchup conditions, and maybe some lateral bipolars as well to see what the beta is.
I will put the different types of possible diodes on our wafer into the list of things to test now! Thanks for the input!
And I agree with Staf that you will want to push the design rules, e.g., long metal, poly, and diffusion strips at close spacing to get a statistical distribution of how often they end up shorting.
Okey
Also long thin poly strips to get a statistical distribution of spot defects large enough to cause an open.
Okey. I keep that in mind. Maybe we limit the length of the poly strip to a value which doesn't show these defects during the test run? I mean we could have multiple lengths of poly on the test wafer. Then we measure them multiple times over the wafer and decide what length is "safe" and what produces defects.
Cheers David
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Tim Edwards