Hi, I just got notified that my NLNet proposal "Langsec in pectore" got approved. What about your proposals? tatzelbrumm
Me too with "Wishbone Streaming Proposal"
Seems, they are going into hardware this time :-)
Regards, Hagen. --- "They who can give up essential liberty to obtain a little temporary safety, deserve neither liberty nor safety." Benjamin Franklin (1775)
Am 20.12.2019 22:48 schrieb Christoph Maier:
Hi, I just got notified that my NLNet proposal "Langsec in pectore" got approved. What about your proposals? tatzelbrumm _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
On 12/20/19, Hagen SANKOWSKI hsank@posteo.de wrote:
Me too with "Wishbone Streaming Proposal"
yes, all six proposals for the libre soc were also approved: a 7th, we have yet to hear from staf (retro-uc, chips4makers), i encouraged him to put one in as well, this is for the cell libraries (SRAM, GPIO, STD) which are essential for any serious processor.
Seems, they are going into hardware this time :-)
in a big way. the basis of the first proposal i put in, back in 2018, was "well duh, if you can't trust the hardware, what's the point of libre software?" and they went, "hmmm..." :)
l.
You now get 7*50kEuro? Or how does that work?! I don't think they'll give you nearly a million Euros?
But if they do: Sharing is caring! ;-)
On Sunday, 22 December 2019 4:51:54 AM HKT Luke Kenneth Casson Leighton wrote:
On 12/20/19, Hagen SANKOWSKI hsank@posteo.de wrote:
Me too with "Wishbone Streaming Proposal"
yes, all six proposals for the libre soc were also approved: a 7th, we have yet to hear from staf (retro-uc, chips4makers), i encouraged him to put one in as well, this is for the cell libraries (SRAM, GPIO, STD) which are essential for any serious processor.
Seems, they are going into hardware this time :-)
in a big way. the basis of the first proposal i put in, back in 2018, was "well duh, if you can't trust the hardware, what's the point of libre software?" and they went, "hmmm..." :)
l. _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
On 12/21/19, David Lanzendörfer david.lanzendoerfer@lanceville.cn wrote:
You now get 7*50kEuro?
not me, the project.
Or how does that work?!
by doing a hell of a lot of work running around like a headless chicken, and finding individuals with a link to the EU who can be part of a team and can put in a "first project". times... seven. eight.
the way it works is that once you have a first successful project (first NLNet Grant approved), you *can* apply for additional projects (up to 3 more, for a total of EUR 200,000). however because we put in *seven* (actually, nine, two of them we withdrew), that was beyond even that limit for one single person. so we set up separate teams (first-time appliers) and they've all been approved.
just need to check with staf to see how he's getting on.
I don't think they'll give you nearly a million Euros?
quarter of a million, and yes, they have approved *different* parts of the project for a total getting on for quarter of a million euros in donations.
one of the key reasons for that is there are side-benefits for *other libre projects*, not just our one. coriolis2 will get some funding for linking to nmigen. nmigen itself will get some funding for integration / use with ASICs [migen can do ASICs, nmigen cannot - only FPGAs]. the wishbone streaming is independent of the project and will "just happen to create some streaming peripherals as examples that will be both generically useful and also speifically useful for the libre soc" and so on and so on.
But if they do: Sharing is caring! ;-)
:)
Hi y'all,
as my participation at the Mumble in 12 1/2 hours from now may be a bit sketchy due to a family event (watching the latest Star Wars movie with my dad and my niece and nephew), here are my most important comments/questions in advance:
On Sat, Dec 21, 2019 at 10:09 PM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On 12/21/19, David Lanzendörfer david.lanzendoerfer@lanceville.cn wrote:
You now get 7*50kEuro?
not me, the project.
Or how does that work?!
by doing a hell of a lot of work running around like a headless chicken, and finding individuals with a link to the EU who can be part of a team and can put in a "first project". times... seven. eight.
the way it works is that once you have a first successful project (first NLNet Grant approved), you *can* apply for additional projects (up to 3 more, for a total of EUR 200,000). however because we put in *seven* (actually, nine, two of them we withdrew), that was beyond even that limit for one single person. so we set up separate teams (first-time appliers) and they've all been approved.
just need to check with staf to see how he's getting on.
I don't think they'll give you nearly a million Euros?
quarter of a million, and yes, they have approved *different* parts of the project for a total getting on for quarter of a million euros in donations.
one of the key reasons for that is there are side-benefits for *other libre projects*, not just our one. coriolis2 will get some funding for linking to nmigen. nmigen itself will get some funding for integration / use with ASICs [migen can do ASICs, nmigen cannot - only FPGAs]. the wishbone streaming is independent of the project and will "just happen to create some streaming peripherals as examples that will be both generically useful and also speifically useful for the libre soc" and so on and so on.
Can we put an <a href> list to our project descriptions somewhere we can all access and find?
How much of Master Luke's [see, I'm already in Star Trek mood] infrastructure is directly useful/adaptible for analog/mixed signal design?
But if they do: Sharing is caring! ;-)
And did they dare to fund the totally crazy Man Going His Own Way who's cooking his own silicon, i.e., did David's proposal get approved?
Brumm. Tatzelbrumm
:) _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
On 12/22/19, Christoph Maier christoph.maier@ieee.org wrote:
Can we put an <a href> list to our project descriptions somewhere we can all access and find?
https://libre-riscv.org/nlnet_proposals/ https://libre-riscv.org/3d_gpu/
How much of Master Luke's [see, I'm already in Star Trek mood] infrastructure is directly useful/adaptible for analog/mixed signal design?
none aaat aaaaaalll. analog/mixed signals were veeery specifically and deeeliberately left *out* of the proposal entirely.
the only analog/mixed signal designing that will occur is for DDR GPIO pads. even analog PLLs is highly likely to get left out, unless someone can demonstrate that it's absolutely essential.
l.
Hello List!
On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote:
none aaat aaaaaalll. analog/mixed signals were veeery specifically and deeeliberately left *out* of the proposal entirely.
the only analog/mixed signal designing that will occur is for DDR GPIO pads. even analog PLLs is highly likely to get left out, unless someone can demonstrate that it's absolutely essential.
It is.
All the Pads have a cut-off frequency somewhere above 100 MHz. When we can run faster someday with smaller nodes, without a PLL, we could not tune up the clock frequency above this cut-off frequency.
Even with our 1 Micron node nowadays a additional PLL is a excellent security feature against Clock Glitching Attacks. The indication, that the PLL lost his lock (lock output gets lost while the attacker glitches the clock line) is used to reset the Chip immediately.
@tatzelbrumm: For the NorthPoint CPU we already proposed we still need a ADC and a DAC. You can earn your street credit nevertheless soon :-)
Regards, Hagen.
On Sunday, December 22, 2019, Hagen SANKOWSKI hsank@posteo.de wrote:
Hello List!
On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote:
none aaat aaaaaalll. analog/mixed signals were veeery specifically and deeeliberately left *out* of the proposal entirely.
the only analog/mixed signal designing that will occur is for DDR GPIO pads. even analog PLLs is highly likely to get left out, unless someone can demonstrate that it's absolutely essential.
It is.
All the Pads have a cut-off frequency somewhere above 100 MHz. When we can run faster someday with smaller nodes, without a PLL, we could not tune up the clock frequency above this cut-off frequency.
ok.
so, from somewhere, we need a libre licensed PLL. is one in development somewhere?
is it worth putting in an extra (small) NLNet grant application for?
l.
Hello Luke.
On 12/22/19 7:04 AM, Luke Kenneth Casson Leighton wrote:
On Sunday, December 22, 2019, Hagen SANKOWSKI <hsank@posteo.de mailto:hsank@posteo.de> wrote:
Hello List! On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote: > none aaat aaaaaalll. analog/mixed signals were veeery specifically > and deeeliberately left *out* of the proposal entirely. > > the only analog/mixed signal designing that will occur is for DDR GPIO > pads. even analog PLLs is highly likely to get left out, unless > someone can demonstrate that it's absolutely essential. It is. All the Pads have a cut-off frequency somewhere above 100 MHz. When we can run faster someday with smaller nodes, without a PLL, we could not tune up the clock frequency above this cut-off frequency.ok. so, from somewhere, we need a libre licensed PLL. is one in development somewhere?
is it worth putting in an extra (small) NLNet grant application for?
The Issue I see - we have to bring back David into the Clean Room first. 'Cause PLLs are quite heavy analog Voodoo stuff and strongly depending on the technology they are using. IMHO we can not re-use a PLL developed for one technology on another technology.
So our goal has to have first the LibreSilicon PDK. Than, with this PDK we can design a PLL which could work for other LibreSilicon PDK users also.
Regards, Hagen.
Hi all I was too busy the last few weeks with working on a project for my best friend, but I've got the grant as well. I'm right now discussing about the conditions of getting the money transferred. The issue right now is, that they would prefer, that I work in an European lab, but I made the oath to myself that if I ever would step a foot back into Europe for longer than a short period of time, it would be either Greece (where the Eresian temple is located) or Portugal (where all the only good things in my life from Switzerland came from in one way or another). So now I'm discussing the possibilities of using the lab in Lisboa, which seems sufficiently equipped to facilitate our research. I'll see where it is leading me.
May Eris, the fairest of all goddesses, be with us. Thai Kallistai
-lev
On Sunday, 22 December 2019 2:15:12 PM HKT Hagen SANKOWSKI wrote:
Hello Luke.
On 12/22/19 7:04 AM, Luke Kenneth Casson Leighton wrote:
On Sunday, December 22, 2019, Hagen SANKOWSKI <hsank@posteo.de
mailto:hsank@posteo.de> wrote: Hello List!
On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote: > none aaat aaaaaalll. analog/mixed signals were veeery specifically > and deeeliberately left *out* of the proposal entirely. > > the only analog/mixed signal designing that will occur is for DDR > GPIO > pads. even analog PLLs is highly likely to get left out, unless > someone can demonstrate that it's absolutely essential. It is. All the Pads have a cut-off frequency somewhere above 100 MHz. When we can run faster someday with smaller nodes, without a PLL, we could not tune up the clock frequency above this cut-off frequency.ok.
so, from somewhere, we need a libre licensed PLL. is one in development somewhere?
is it worth putting in an extra (small) NLNet grant application for?
The Issue I see - we have to bring back David into the Clean Room first. 'Cause PLLs are quite heavy analog Voodoo stuff and strongly depending on the technology they are using. IMHO we can not re-use a PLL developed for one technology on another technology.
So our goal has to have first the LibreSilicon PDK. Than, with this PDK we can design a PLL which could work for other LibreSilicon PDK users also.
Regards, Hagen.
Ah
And in case that sounded a bit religiously fanatic... ^^' I'm right now ducking scared about what will be the final condition from NLNet for getting the funding. So I'm basically at a point where I only can choose one or another option and hope for the best. In such cases, praying is a good option ^^'
-lev
On Monday, 23 December 2019 4:49:46 AM HKT David Lanzendörfer wrote:
Hi all I was too busy the last few weeks with working on a project for my best friend, but I've got the grant as well. I'm right now discussing about the conditions of getting the money transferred. The issue right now is, that they would prefer, that I work in an European lab, but I made the oath to myself that if I ever would step a foot back into Europe for longer than a short period of time, it would be either Greece (where the Eresian temple is located) or Portugal (where all the only good things in my life from Switzerland came from in one way or another). So now I'm discussing the possibilities of using the lab in Lisboa, which seems sufficiently equipped to facilitate our research. I'll see where it is leading me.
May Eris, the fairest of all goddesses, be with us. Thai Kallistai
-lev
On Sunday, 22 December 2019 2:15:12 PM HKT Hagen SANKOWSKI wrote:
Hello Luke.
On 12/22/19 7:04 AM, Luke Kenneth Casson Leighton wrote:
On Sunday, December 22, 2019, Hagen SANKOWSKI <hsank@posteo.de
mailto:hsank@posteo.de> wrote: Hello List!
On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote: > none aaat aaaaaalll. analog/mixed signals were veeery > specifically > and deeeliberately left *out* of the proposal entirely. > > the only analog/mixed signal designing that will occur is for DDR > GPIO > pads. even analog PLLs is highly likely to get left out, unless > someone can demonstrate that it's absolutely essential. It is. All the Pads have a cut-off frequency somewhere above 100 MHz. When we can run faster someday with smaller nodes, without a PLL, we could not tune up the clock frequency above this cut-off frequency.ok.
so, from somewhere, we need a libre licensed PLL. is one in development somewhere?
is it worth putting in an extra (small) NLNet grant application for?
The Issue I see - we have to bring back David into the Clean Room first. 'Cause PLLs are quite heavy analog Voodoo stuff and strongly depending on the technology they are using. IMHO we can not re-use a PLL developed for one technology on another technology.
So our goal has to have first the LibreSilicon PDK. Than, with this PDK we can design a PLL which could work for other LibreSilicon PDK users also.
Regards, Hagen.
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Christoph Maier -
Christoph Maier -
David Lanzendörfer -
Hagen SANKOWSKI -
Luke Kenneth Casson Leighton