Hello,
I had a quick look at the current PearlRiver design(s). I also see layout not schematics or netlists. Do you plan to simulatie your measurement procedures before actually manufacturing the wafer ?
Normal design procedure for analog (test) circuits is first do schematic capture, simulate the test procedure and then make layout according to schema and make it LVS (layout-versus-schematic) clean.
Specifically for the L500_MOSFET_aligning structure which is indicated to also be used for measuring resistance and capacitance. To save pins I see a lot of pins are shared. For example I see that the middle pin is both connected to NWELL as to PSUB/PWELL which seems dangerous to me. In general I see that almost all of the pins are in one way connected to NWELL or PSUB/PWELL and basically shorted with other pins through these wells and also metal1. So I am wondering which resistances you actually try to measure here.
greets, Staf.
Hey Staf Yeah. Hagen has done some schematics and simulations as well, but he hasn't yet pushed it as far as I understood him. This is supposed to contain an overview over all the test structures: https://github.com/chipforge/PearlRiver/tree/master/Documents/LaTeX
We now have set up a video conferencing tool on https://meet.lanceville.hk and I was hoping we could start streaming on Youtube how we discuss exactly stuff like the content of the documentation and so on.
Cheers David
I had a quick look at the current PearlRiver design(s). I also see layout not schematics or netlists. Do you plan to simulatie your measurement procedures before actually manufacturing the wafer ?
Normal design procedure for analog (test) circuits is first do schematic capture, simulate the test procedure and then make layout according to schema and make it LVS (layout-versus-schematic) clean.
Specifically for the L500_MOSFET_aligning structure which is indicated to also be used for measuring resistance and capacitance. To save pins I see a lot of pins are shared. For example I see that the middle pin is both connected to NWELL as to PSUB/PWELL which seems dangerous to me. In general I see that almost all of the pins are in one way connected to NWELL or PSUB/PWELL and basically shorted with other pins through these wells and also metal1. So I am wondering which resistances you actually try to measure here.
Hello Staf.
First, I like to thank that you looked at the layout. Second, you are right in your observations.
Yes, the L500_MOSFET_aligning MOSFET-like structure shares the same Ground-Pad in the middle. And, the PAD which drives the Poly-Gate on the MOSFET-like structure is also shared with a DRAIN-/SOURCE-stripe.
If you look deeper into the structure (which I adapt from a german textbook [0]), you see that the DRAIN- and SOURCE stripe is shorted to one contact. So, the structure looks similar to a MOSFET transistor, but it isn't, and can not work as a transistor. We like to - see how good align we can different mask (esp. needed for MOSFETS), therefor they are rotated by 90 degree. - measure long, long nimplant/pimplant stripes (150 um long, with minimal GATE-size of 1 um) for resistance. - measure, if the Mask alignment is not so perfect, how this impacts the nimplemant/pimplemant resistance.
BTW, between shared PADs, the internal structure looks like a Resistor (the DRAIN-/SOURCE-stripes on one MOSFET-like structure) in parallel to Capacitor (the long Poly-Si GATE stripe of another MOSFET-like structure).
Regarding your concern, we like to measure with a 4-pin needle probe. So, usually we stimulate two PADs with current / voltage and measure on both others current / voltage. My expectation is, that there are no trigger for latch-up or other parasitic effects. And, currently, we can not simulate the structures as we are missing the first values. After measuring resistance and capacitance, we get the values for the BSIM3v3 Spice-Modell and can simulate more productive structures.
And yes, I am aware of my duty to document all thoughts around the test structures :-)
Regards, Hagen.
[0] https://www.amazon.de/Proze%C3%9Ftechnologie-Fertigungsverfahren-Integrierte...
--- "They who can give up essential liberty to obtain a little temporary safety, deserve neither liberty nor safety." Benjamin Franklin (1775)
Am 03.08.2018 13:28 schrieb Staf Verhaegen:
Hello,
I had a quick look at the current PearlRiver design(s). I also see layout not schematics or netlists. Do you plan to simulatie your measurement procedures before actually manufacturing the wafer ?
Normal design procedure for analog (test) circuits is first do schematic capture, simulate the test procedure and then make layout according to schema and make it LVS (layout-versus-schematic) clean.
Specifically for the L500_MOSFET_aligning structure which is indicated to also be used for measuring resistance and capacitance. To save pins I see a lot of pins are shared. For example I see that the middle pin is both connected to NWELL as to PSUB/PWELL which seems dangerous to me. In general I see that almost all of the pins are in one way connected to NWELL or PSUB/PWELL and basically shorted with other pins through these wells and also metal1. So I am wondering which resistances you actually try to measure here.
greets, Staf.
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hagen, I did not look carefully enough and thought all metal1 was shorted between center ground pin and the other pins.I know principle of 4- point measurement also called force/sense. I have problem figuring out how it is applicable to this design. Could you give example for one of the structures which pads are used for force and which for sense ?You may not be able to simulate structure exactly but you can use some assumed values to see if measurement procedure will actually work. Best to include all (parasitic) junctions in such simulation. Speaking from experience they often can cause problems when sharing pins when they are unwanted biased in forward. greets,Staf. Hagen SANKOWSKI schreef op vr 03-08-2018 om 14:48 [+0200]:
Hello Staf.
Yes, the L500_MOSFET_aligning MOSFET-like structure shares the same Ground-Pad in the middle. And, the PAD which drives the Poly-Gate on the MOSFET-like structure is also shared with a DRAIN-/SOURCE-stripe.
If you look deeper into the structure (which I adapt from a german textbook [0]), you see that the DRAIN- and SOURCE stripe is shorted to one contact. So, the structure looks similar to a MOSFET transistor, but it isn't, and can not work as a transistor. We like to
- see how good align we can different mask (esp. needed for
MOSFETS), therefor they are rotated by 90 degree.
- measure long, long nimplant/pimplant stripes (150 um long, with
minimal GATE-size of 1 um) for resistance.
- measure, if the Mask alignment is not so perfect, how this impacts
the nimplemant/pimplemant resistance.
BTW, between shared PADs, the internal structure looks like a Resistor (the DRAIN-/SOURCE-stripes on one MOSFET-like structure) in parallel to Capacitor (the long Poly-Si GATE stripe of another MOSFET-like structure).
Regarding your concern, we like to measure with a 4-pin needle probe. So, usually we stimulate two PADs with current / voltage and measure on both others current / voltage. My expectation is, that there are no trigger for latch-up or other parasitic effects. And, currently, we can not simulate the structures as we are missing the first values. After measuring resistance and capacitance, we get the values for the BSIM3v3 Spice-Modell and can simulate more productive structures.
And yes, I am aware of my duty to document all thoughts around the test structures :-)
Regards, Hagen.
[0] https://www.amazon.de/Proze%C3%9Ftechnologie-Fertigungsverfahren-Integrier te-Mos-Schaltungen-Mikroelektronik/dp/3540176705
"They who can give up essential liberty to obtain a little temporary safety, deserve neither liberty nor safety." Benjamin Franklin (1775)
Am 03.08.2018 13:28 schrieb Staf Verhaegen:
Hello,
I had a quick look at the current PearlRiver design(s). I also see layout not schematics or netlists. Do you plan to simulatie your measurement procedures before actually manufacturing the wafer ?
Normal design procedure for analog (test) circuits is first do schematic capture, simulate the test procedure and then make layout according to schema and make it LVS (layout-versus-schematic) clean.
Specifically for the L500_MOSFET_aligning structure which is indicated to also be used for measuring resistance and capacitance. To save pins I see a lot of pins are shared. For example I see that the middle pin is both connected to NWELL as to PSUB/PWELL which seems dangerous to me. In general I see that almost all of the pins are in one way connected to NWELL or PSUB/PWELL and basically shorted with other pins through these wells and also metal1. So I am wondering which resistances you actually try to measure here.
greets, Staf.
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hi Hagen So now after going through your layout and researching the layers it turns out we can perfectly map your layout to our process: https://www.eda.ncsu.edu/wiki/MOSIS_Layers
The only thing which is missing are pwells.
After lots of thinking I just realized that this is the only problem. Because the active area is way smaller than the nwell/pwell anyway we're not in any danger of building junctions outside of the island.
Also: When we run the STI etching after diffusion any offset in alignment won't be a problem because of the spacing between the active area and the outer edge of the nwell/pwell. So we can just expose the pwell and nwell mask for the STI isolation etch.
I've started to add pwells, please have a look at my pull request: https://github.com/chipforge/PearlRiver/pull/2
Cheers David
I did not look carefully enough and thought all metal1 was shorted between center ground pin and the other pins. I know principle of 4-point measurement also called force/sense. I have problem figuring out how it is applicable to this design. Could you give example for one of the structures which pads are used for force and which for sense ? You may not be able to simulate structure exactly but you can use some assumed values to see if measurement procedure will actually work. Best to include all (parasitic) junctions in such simulation. Speaking from experience they often can cause problems when sharing pins when they are unwanted biased in forward.
Hello David!
On 08/04/2018 05:59 PM, David Lanzendörfer wrote:
I've started to add pwells, please have a look at my pull request: https://github.com/chipforge/PearlRiver/pull/2
Done. And I add the pwells for other Library/magic cells also.
Best Regards, Hagen.
Hi
Done. And I add the pwells for other Library/magic cells also.
Great! Thanks! ^^ I'm still working on fixing the process steps according to Shuyun. The Aluminum thickness will be 600nm BTW. With that you can already calculate the resistivity of the wires and the vias! And with a lot of Matlab maybe even the capacity ^^'
Cheers David
Hi I've just realized while hacking at the script to generate the GDS files for ordering the masks that we don't have a glass layer planned yet ^^' (It's in the layout) I would have to add another step/mask in order to deposit another layer of silicon-oxide for that at the end and etch it.
Is it crucial to have glass or can we just skip it for now? ^^'
Cheers David
Am Dienstag, 7. August 2018, 23:22:29 HKT schrieb Hagen SANKOWSKI:
Hello David!
On 08/04/2018 05:59 PM, David Lanzendörfer wrote:
I've started to add pwells, please have a look at my pull request: https://github.com/chipforge/PearlRiver/pull/2
Done. And I add the pwells for other Library/magic cells also.
Best Regards, Hagen.
Hello David.
On 08/10/2018 02:43 PM, David Lanzendörfer wrote:
I've just realized while hacking at the script to generate the GDS files for ordering the masks that we don't have a glass layer planned yet ^^' (It's in the layout) I would have to add another step/mask in order to deposit another layer of silicon-oxide for that at the end and etch it.
Is it crucial to have glass or can we just skip it for now? ^^'
Well, the Test Pad cells using the GLASS layer :-)
Skip the GLASS layer for PearlRiver.
This saves money for the mask and we do not have advantages of using GLASS.
Later we should use passivation for better reliability of the chips.
Regards, Hagen.
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