Hi all I've just realized that we need CMP because there is just no better way to fill out the trenches in order to avoid parasitic NMOS transistors occuring when the gate is too close to the p-substrate... I'll check with HKUST in order to verify the numbers given by them. Because if their CMP really is 5um in variation, we have a big problem now...

Cheers David

On Saturday, 24 March 2018 4:54:23 PM HKT David Lanzendörfer wrote:

Hi During the meeting we found out that we don't need a nitride hard mask but can use an oxide mask in order to etch silicon with a plasma etcher. Also I've found out that the variation of the CMP machine is terrible (~5um!) Now that we have oxide should we just skip the CMP step and just grow our process oxide for the n-well/p-well construction over it?

@Staf: Can you maybe join this weeks mumble meeting and give some feedback? I'll update the document until then, so that we can discuss it.

Cheers David