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Test wafer
by David Lanzendörfer 13 Mar '18

13 Mar '18

Hi We should start drawing the test wafer components. We can use Magic already until we get around and fix up QtFlow and it's Magic editor component. We can make our own "pad frame" which for now just consists of passive aluminum bonding pads and then we hook up all our testing components to it within. I already started defining some of the test structures conceptionally in the chapter "Testing". That's something where Hagen also could join the party, and you too Tim ;-) For quicker rendering and editing I've split out the chapter into the file here https://github.com/leviathanch/libresiliconprocess/blob/master/documentatio… https://github.com/leviathanch/libresiliconprocess/blob/master/documentatio… Also some input: Feel free to add more possible diode geometries you would suggest to include into the test wafer for measurement. And again: If someone wants to come to Hong Kong and help in the clean room, feel free! Cheers David

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Finally! Solved the issue with spacers and silicide
by David Lanzendörfer 10 Mar '18

10 Mar '18

Hi all I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers. Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers? Cheers David

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Sunday
by David Lanzendörfer 09 Mar '18

09 Mar '18

Hi I'm still in the process of recalculating the new process parameters because of the switch to polysilicon, and also I need to decide on the machines for the last few steps. Who's all joining in this Sunday for the mumble conference? Cheers David

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ESD
by David Lanzendörfer 08 Mar '18

08 Mar '18

Hi I've just found this article here: https://read01.com/gO8jKA.html#.WqGpRXVBiV4 We have to do this! https://i2.read01.com/SIG=20vgqvc/3046575a433439423531.jpg Cheers David -- Best regards CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen

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Poly vs. Aluminum
by David Lanzendörfer 06 Mar '18

06 Mar '18

Hi folks Going through the process over and over again I have to appreciate Stafs input on the gate alignment. Already with 1um it's very difficult to get a proper alignment of the overlap of the drain/source and the gate. Maybe we should consider poly silicon after all? (It won't affect the layout) Cheers David

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Numbers
by David Lanzendörfer 05 Mar '18

05 Mar '18

Hi I'm reworking the transistor characteristics formulas during the next few days, because if you look at the wxMaxima worksheets and plot the threshold functions, they seem to be kind of off... Which means, I'll literally go over the books again there and see what I'm doing wrong. I've got some suspicions, but I postpone that, so that I can get some sleep before the sun comes out again ^^' @Staf: I've now removed the etching step for the hard mask removal and replaced it with a CMP step. The machine I've linked in the step can polish away nitride and oxide at once. Cheers David

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Logic levels
by David Lanzendörfer 05 Mar '18

05 Mar '18

Hi Okey. I just realized that I was totally "optimizing" for things which don't make sense... Of course the pull up has to pull up, as soon as 0.8V is reached and the pull down needs to pull down at 2V, not the other way around... I mixed up numbers. Seems I'm stressing myself because and get totally confused as soon as people start looking me and expect something to see ^_^' Yeah. Now finally I agree. 0.8V and -0.8V are more than enough for the transistors. Cheers! David

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The Spice Model BSIM3v3 for MOSFETs
by Hagen SANKOWSKI 05 Mar '18

05 Mar '18

There are a couple of MOSFET Models available, the last one I came across was BSIM4 (for deep-sub-Mircon <100 nm) and BSIM3 which ought to be good enough down to 180 nm. @David, your Simulator uses the most simplest (and fastest) Model which is know as a first generation model for default. So, the 3rd generation model, quite more complicated has a couple of more parameters to tune. Here is the documentation from ngspice, btw. the best FOSS spice simulator we can use. http://ngspice.sourceforge.net/external-documents/models/bsim330_manual.pdf We need reasonable values for *all* parameters!

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Question: Production time vs. power efficiency
by David Lanzendörfer 05 Mar '18

05 Mar '18

Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much lower, which will give less losses in the device. Cheers David

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F.Y.I. https://vcs.in-berlin.de/chipforge_stdcelllib/index
by Hagen SANKOWSKI 05 Mar '18

05 Mar '18

Dear List Members. We (hopefully) all like to be Open Source. IMHO this also means to handle the background information why we doing what on that way. While developing the Standard Cell Library often I came across the issue, how to communicate the design decision I am always taking there. In case of the Standard Cell Library there are e.g. topics like: = Why the number of stacked transistors becomes an important issue? = Why all the Textbooks handle only a dozen Cells and we like to have much more? = Why IO-Cells are so underestimated? = What are alternatives? So, to handle all this questions I already set up a Fossil Repository [0] where I try to explain all this stuff. Please note the link in the subject line. And yes, there is still a lot of work to do. Do not be afraid of asking stupid questions regarding the Standard Cell Library here on the list - I'll to try to answer them and publish explanations on this Wiki pages. Regards, Hagen. [0] https://en.wikipedia.org/wiki/Fossil_(software)

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