- Libresilicon-developers - libresilicon.com

Documentation on testing
by David Lanzendörfer 10 May '18

10 May '18

Hi I've drawn some more graphics but I'm still lacking text and so on: https://github.com/leviathanch/libresiliconprocess/blob/master/process_test… @Hagen: If you like you can also give me text would like to add in German and I translate it into English Cheers David

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LibreSilicon Hackathon Dresden
by Hagen SANKOWSKI 09 May '18

09 May '18

------------------------- - English version below - ------------------------- Hallo! Jetzt ist fix - Danke an alle, die sich am Doodle Request beteiligt haben! Wir wollen die bereits im akademischen Umfeld existierende Software sichten/entstauben/verbessern. JEDER, der sich für das Thema "freies Silicium" interessiert, ist herzlich eingeladen zum mitzugestalten. Kommt und helft mit; egal, ob Ihr Zeit für alle drei Tage, zwei Tage oder eben auch nur einen Tag habt. Unser Hackathon ist öffentlich - hier also die Koordinaten: WANN: ----- vom 19. bis 21.Mai 2018 WO: --- Zentralwerk, Riesaer Straße 32, 01127 Dresden, Sachsen, Germany AGENDA am 19.Mai: ----------------- 12.00 - 13.00 Willkommen, Orga 13.00 - 14.00 Einführung ins Thema 14.00 - open end Hack, Eat, Sleep, Repeat AGENDA am 20. & 21.Mai: ----------------------- t.b.d. Hack, Eat, Sleep, Repeat Das Event wird vor Ort ausgeschildert sein. Wer sich für das offizielle Hackathon T-Shirt interessiert kann mir (möglichst bis heute 20.00 UTC) seine Größe per Email mitteilen - die T-Shirts fallen wohl kleiner aus. Wir freuen uns auf Eurer (hoffentlich zahlreiches) Erscheinen! Hagen Sankowski ------------------- - English version - ------------------- Hello! Now it is fixed - Thanks to anyone who took part on the Doodle Requests! We like to find/rectify/enrich Programs from the mostly academic area. EVERYBODY, who is interested in the "free Silicon" gets a warm welcome. Help us if you like, whatever you have time for three days, two days or even one day. Our Hackathon is public - here are the coordinates: WHEN: ----- from May 19 to May 21, 2018 WHERE: ------ Zentralwerk, Riesaer Straße 32, 01127 Dresden, Sachsen, Germany AGENDA on May 19: ----------------- 12.00 - 13.00 Welcome, Orga 13.00 - 14.00 Introduction into Topic 14.00 - open end Hack, Eat, Sleep, Repeat AGENDA on May 20 and May 21: --------------------------- t.b.d. Hack, Eat, Sleep, Repeat The event will be signposted inside. Who likes to get the official Hackathon T-Shirt, please drop me an email (hopefully today till 20.00 UTC) with your size - the shirts are probably smaller than expected. We are pleased to see you! Hagen Sankowski

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Lightweight PDFs
by David Lanzendörfer 08 May '18

08 May '18

Hi everyone I've now split up the one big 20 MB PDF in smaller subdocuments. The documents now load much much faster: https://github.com/leviathanch/libresiliconprocess/blob/master/process_step… @Hagen: I've finished hacking your test structure cross sections for the ESD circuit into LaTeX. (Schematics will follow, I was busy also with getting the issues fixed Mohamed reported) https://github.com/leviathanch/libresiliconprocess/blob/master/process_test… Maybe you wanna hack some text into the LaTeX files under the tikz graphics? Cheers David

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Website
by David Lanzendörfer 07 May '18

07 May '18

Hi everyone I've updated the project website a bit further under http://libresilicon.com/ As you can see there is much more text there and the text now better reflects the aim of our project. Please review the content and come back to me in case you've got pull requests for the website. The repository for the page is under: https://github.com/leviathanch/leviathanch.github.io Cheers David

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QtFlow Debian/Ubuntu packages
by David Lanzendörfer 06 May '18

06 May '18

Hi I've now successfully built the Debian and Ubuntu package for QtFlow. The repositories are here: https://download.opensuse.org/repositories/home:/leviathanch:/debian-asic/ For instance for Debian: https://download.opensuse.org/repositories/home:/leviathanch:/debian-asic/D… Cheers David

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REMINDER - Tool Chain Hackathon
by Hagen SANKOWSKI 06 May '18

06 May '18

- English Version below - Hallo. Ein kleines Update: die beiden Doodle Pull Requests für Ort und Zeit laufen noch. Dresden - https://doodle.com/poll/hv3ezxtak769g9d5 Berlin - https://doodle.com/poll/yhe3sxqabdg2kwfg Die Tendenz geht derzeit an Dresden zu Pfingsten. Tragt Euch bitte ein, wenn Ihr daran teilnehmen wollt! DRINGEND! Auf der Hackathon-Agenda stehen: - Einführung in den ASIC Design Flow, - Code Basis von existierenden FOSS Tools ansehen, - Brainstroming zu neuen, moderneren Ansätzen, - Hacken, Essen, Schlafen, Duschen, Hacken.. Gruss, Hagen Sankowski - English Version - Hello. A small update: both Doodle Pull Requests for place and time are still running. Dresden - https://doodle.com/poll/hv3ezxtak769g9d5 Berlin - https://doodle.com/poll/yhe3sxqabdg2kwfg Tendency currently shifts to Dresden at Pentecost / Whitsday. Please vote at Doodle, who will take part! URGEND! Well, on the Agenda for the Hackathon already are: - Introduction to the ASIC design flow, - Checking the code base of existing FOSS tools, - Brainstoriming for better approaches, - Hacking, Eating, Sleeping, take a Shower, and repeat. Regards, Hagen Sankowski

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Reminder - next Mumble Session on May 6, 2018, 21.00 HKT
by Hagen SANKOWSKI 05 May '18

05 May '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, May 6 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - the hackathon for the tool chain - license proposals - other stuff around libre silicon Happy to hear from you! Hagen

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QtFlow compilation errors
by David Lanzendörfer 05 May '18

05 May '18

Hi I now get compilation errors as well with the most recent gcc, I'm working on fixing it and will then publish a .deb and .rpm as promised. Sorry for the delays. Cheers David

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Tool Chain Hackathon
by Hagen SANKOWSKI 01 May '18

01 May '18

Hello List! As you might notice I am organizing currently a Libre Silicon Hackathon. We like to polish up the Tool Chain, which David already forked on github. [0] Well, this seems to be something more software-based, for everybody which is not so familiar with the ASIC design flow. I like to put this items on the agenda for the Hackathon - introduction into the ASIC design flow - checking the code base of FOSS tools which are already there - brainstorming new approaches for more modern tooling - hacking, eat, sleep, repeat While looking for a nice space, it is difficult to find a date in May. There are some holidays and some bigger events like the Gulaschprogrammiernacht. [1] Well, I got already one feedback from Dresden over Whitsuntide / Pentecost and set up a doodle poll request for that location. [2] Other locations should/might follow. BTW, I like to provide a cool Hackathon T-Shirt for every participant also :-) Regards, Hagen Sankowski [0] https://github.com/leviathanch/qtflow [1] https://entropia.de/GPN18 [2] https://doodle.com/poll/hv3ezxtak769g9d5

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Re: [Libre-silicon-devel] Standardized Data Structures Lef/Def routines
by Hagen SANKOWSKI 28 Apr '18

28 Apr '18

Hello Paul. My notes below. On 04/28/2018 06:01 AM, p4w5 wrote: > Before dealing with this I would opt to have some common core dealing > with lefdef reading and writing. Is there maybe already some tool doing > this? > In the last week I started going through the lefdef ref manual 5.8 and > to manually parse lef files into some c++ structs, see[1] to have a look > yourself. From quite some big lef files it already can parse >90% the > mayor chunck. Being quite uncommented and not tougth through to much, > but before wasting more time on this I wanted to get some feedback. > > Is the general lefdef-lib thing a idea worth spending more energy on? Is > there already another attempt to do so in progress? Yes, you are right, the tools mostly dealing with LEF/DEF formats somehow. But for me, LEF/DEF is nothing more than an export format. Let's look at the dataflow for the ASIC design to describe why I think so. First, someone is writing the RTL [0] code, mostly in Verilog [1], VHDL [2] or any other Hardware Description Language which is useful for that. Than a Synthesizer tool [3] translates this behavioral description into a so called netlist [4]. While the netlist is nothing more than a list of dedicated primitives like gates, Latches and other cells, this Synthesis tool already needs a bunch of information (even the timing/delays) about the primitives which are should used later in the layout. Yosys [5] as an FOSS synthesis tools uses the so called BLIF format [6] for that. Additionaly, someone want to add the stuff for testability here. Now, the netlist represents somehow the RTL design with primitives from the Standard Cell Library (BTW, I am developing the Standard Cell Library here [7]). Second, the designer now starts the layout by assigning the values for size of the die, doing all the floor planning stuff. [8] Here the physical sizes / layer of the primitives / Standard Cells are very useful to calculate the space, that is the point where LEF [9] and DEF [10] cames in. Both formates are just layer informations - they are not suitable for the synthesis step before. Third, the Place and Routing step needs the exact timing of the primitives / cells again while re-iterating many times through the netlist and find the best placement and routing regarding the constraints which already was used for the synthesis. And this step should use already technology information based on Resistance and Capacitance (every line is a RC-circuit [11] which produces a delay), called wireload model. Long distances producing longer delays, to short lines are also avoidable regarding the Setup- and Hold-Violations [12] Forth, while the design matches all constraints (in the meaning of operations frequency for every part) etc, now the layout of the die, the placement of the IO-Cells, the clock tree, the placed cells and all the wires are now transformed to the GDSII file [13] which goes to the foundry. So, from LEF / DEF to GDSII is the last step. IMHO, we should look at the ALF file format also [14] for the library. There are all informations we are needing for all steps, from synthesis to place'n'route and GDSII generation in one file format. This pure ASCII file format became a IEEE 1603 and IEC 62265 standard. But this format is dedicated for library elements (the Standard Cell Lib) - I am not sure we can use / re-use / expand it to our internal file format of the layout tool chain. I guess, we should use it for the layout also, keeping all the information together in one file format which could make a difference for our FOSS tools. All the tools for ASIC layout are quite old and limited; using cell delays (aka timing) or physical parameters of the process for better results are difficult with that old tools. While using ALF even for the layout, we are able to press the button and generate export formats (for user tools). On my list there are already as mentioned - BLIF - LEF / DEF and not mentioned - SDF. [15] I am currently organizing the hackathon for the tool chain - I'll send out today more about that. Let's make it better, let's make a difference! Regards, Hagen Sankowski [0] https://en.wikipedia.org/wiki/Register-transfer_level [1] https://en.wikipedia.org/wiki/Verilog [2] https://en.wikipedia.org/wiki/VHDL [3] https://en.wikipedia.org/wiki/Logic_synthesis [4] https://en.wikipedia.org/wiki/Netlist [5] http://www.clifford.at/yosys/ [6] http://bear.ces.cwru.edu/eecs_cad/sis_blif.pdf [7] https://github.com/chipforge/stdcelllib [8] https://en.wikipedia.org/wiki/Floorplan_(microelectronics) [9] https://en.wikipedia.org/wiki/Library_Exchange_Format [10] https://en.wikipedia.org/wiki/Design_Exchange_Format [11] https://en.wikipedia.org/wiki/RC_circuit [12] https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Timing_parameters [13] https://en.wikipedia.org/wiki/GDSII [14] https://en.wikipedia.org/wiki/Advanced_Library_Format [15] https://en.wikipedia.org/wiki/Standard_Delay_Format

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