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Design rules
by David Lanzendörfer 01 Aug '19

01 Aug '19

Hi everyone Magic uses the MOSIS design rules by default (on which we've built our rules). The minimum width and length for contacts (including poly contact) is 4 lambda (2 microns side length). So either I hack Magic in a way that it requires less height/length for the vias of LibreSilicon or we try to use 2 microns side length. Any inputs? -lev

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Re: [Libre-silicon-devel] Fwd: GitHub and Trade Controls
by Zhiyang Ong 28 Jul '19

28 Jul '19

G'Day contributors of the Libre-silicon project, Thank you so much for supporting Dr./Mr. Mohammad Amin Nili, and others, who can have their access to GitHub (not just the Libre-silicon project repository) or another source-code-hosting facility restricted. We greatly appreciate it. Regards, Zhiyang On Fri, Jul 26, 2019 at 10:08 PM David Lanzendörfer <leviathan(a)libresilicon.com> wrote: > > Hi > > Perhaps you can mirror the libre* related projects on that server ? > Lots of them are already there: > https://redmine.libresilicon.com/projects > > > It might also be a good idea to get in touch with EFF, to at least > > point out this issue. > Be my guest ;-) > > -lev_______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers(a)list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers

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Fwd: GitHub and Trade Controls
by Mohammad Amin Nili 27 Jul '19

27 Jul '19

How could it be even possible?!!! Sanctions imposed by U.S. gov even could affect on open source community?! Is it possible for the list to create a personal repository? > Begin forwarded message: > > From: GitHub <noreply(a)github.com> > Subject: GitHub and Trade Controls > Date: July 26, 2019 at 9:46:37 PM GMT+4:30 > To: manili > > Due to U.S. trade controls law restrictions, your GitHub account has been restricted. > For individual accounts, you may have limited access to free GitHub public repository > services for personal communications only. Please read about GitHub and Trade Controls at > https://help.github.com/articles/github-and-trade-controls for more information. >

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Reminder - Next Mumble session on Sunday, 28/07/2019, 21.00 HKT
by reminder＠libresilicon.com 27 Jul '19

27 Jul '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, 28/07/2019, at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. Thanks for the attention!

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Reminder - Next Mumble session on Sunday, 21/07/2019, 21.00 HKT
by reminder＠libresilicon.com 20 Jul '19

20 Jul '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, 21/07/2019, at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. Thanks for the attention!

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Documentation
by David Lanzendörfer 14 Jul '19

14 Jul '19

Hi I've update the process documentation. The graphics are still work in progress, but I think the text should now be ok. Please have a look at it and lets discuss it tonight, 9pm HKT in Mumble. Cheers -lev PS: I also pushed the changes already to GIT

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PMOS characteristization
by Éger Ferenc 13 Jul '19

13 Jul '19

Hello Everyone, Today I figured out how to extract the drain current of the "real" PMOS from the currently available "leaky" measurements. The process is: 1. Take "thermally_compensated". 2. Compute the slope of the curve (i.e. leakage conductance) by averaging dY/dX between -0.5 and 0V (where "real") drain current is expected to be zero. 3. Based on that, calculate the D-G leakage current (linear resistive case). 4. Subtract the leakage from the measurement data. [image: image.png] The results show clearly a quadratic Id-Vgs behavior and a Vth around 0.6V. The spreadsheet containing the calculation is attached. According to David, this was taken at a PMOS L10/W10 cell. Unfortunately, for the NMOS results, the instrument went off-scale around Vgs=0V, so the neccessary fix points cannot be acquired. Regards, Ferenc

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AI builds chips
by David Lanzendörfer 12 Jul '19

12 Jul '19

Hi This article looks really interesting: https://www.technologyreview.com/lists/innovators-under-35/2019/visionary/ azalia-mirhoseini/ Maybe we could use that AI and give it the LibrePDK in order to make us IP cores ^^ -lev

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RISC-V Foundation Announces Ratification of the RISC-V Base ISA and Privileged Architecture Specifications
by Hagen SANKOWSKI 12 Jul '19

12 Jul '19

Hello List! As you might know, we also have a RISC-V implementation on our agenda. Here are good news from the RISC-V Foundation: https://riscv.org/2019/07/risc-v-foundation-announces-ratification-of-the-r… Best Regards, Hagen.

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Update: RCL cross verification
by David Lanzendörfer 09 Jul '19

09 Jul '19

Hi everyone So I've had a mail exchange and we can go through our recent status together with the engineers at RCL, as soon as we're done cleaning up everything. Tasks: a) We've gotta rework PearlRiver, so that it's in accordance with the new design rules which arose from the R&D. Mainly: Contact holes should all have the same size because the dry etching time is varying with the area of the contact hole. So the yield goes into the basement when the vias/contacts in the oxide all have different dimensions. b) Also I'm right now cleaning up the documentation for the process so that it reflects what I've actually done the past year in the lab. c) After we're done with it, we'll do some legal stuff and can most likely make a test run. I don't think the engineers checking our process will tell us to fuck off, since we're not just a bunch of bat shit crazy dilettantes but actually know what we're doing and I believe this will be clearly reflected in the artwork (updated PearlRiver GDS files) and updated documentation. So we're on a good way. -lev

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