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Reminder - Next Mumble session on Sunday, 17/11/2019, 21.00 HKT
by reminder＠libresilicon.com 16 Nov '19

16 Nov '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, 17/11/2019, at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. Thanks for the attention!

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Reminder - Next Mumble session on Sunday, 10/11/2019, 21.00 HKT
by reminder＠libresilicon.com 09 Nov '19

09 Nov '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, 10/11/2019, at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. Thanks for the attention!

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Test
by David Lanzendörfer 07 Nov '19

07 Nov '19

Does this still work? -lev

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PAD Cells
by Hagen SANKOWSKI 06 Nov '19

06 Nov '19

Hello List! While doing some homework regarding our PAD cells, I once again looked into the MOSIC Design Rules for Scalable CMOS [0]. Out of Rule Set 10.x we get the mimimum grid for bonding pad areas with 102 micron. So my question is here, do somebody has access to bonding machines and their documentation and can provide the grid of bonding pad areas this machines usually can handle? Is this 95u/100u as I still remember? Or are this machines already in the milli-inch-measured domain, e.g. 4 mil for 101.6u? Curious, Hagen. [0] https://www.mosis.com/files/scmos/scmos.pdf -- support LibreSilicon to get back into the Clean Room https://www.gofundme.com/f/libresilicon-cleanroom-rent

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Help - proofreading Standard Cell Configuration File
by Hagen SANKOWSKI 06 Nov '19

06 Nov '19

Hello list! Today I wrote a template to configure the Standard Cell Library build process in a TOML file [0]. Well, I like to invite you - with obviously better english language skills than me - to proofread this work [1]. Any feedback welcome! Best Regards, Hagen. [0] https://en.wikipedia.org/wiki/TOML [1] https://github.com/chipforge/StdCellLib/blob/master/Templates/TOML/LS1u_std… -- support LibreSilicon to get back into the Clean Room https://www.gofundme.com/f/libresilicon-cleanroom-rent

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A warm welcome
by David Lanzendörfer 05 Nov '19

05 Nov '19

Hi all A warm welcome to our newest recruit in the effort to create 100% free and open source silicon. All say hi to Djamel Dellaa who's interested into using our node together with the layout tool GLADE. Cheers -lev

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Reminder - Next Mumble session on Sunday, 03/11/2019, 21.00 HKT
by reminder＠libresilicon.com 02 Nov '19

02 Nov '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, 03/11/2019, at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. Thanks for the attention!

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Reminder - Next Mumble session on Sunday, 27/10/2019, 21.00 HKT
by reminder＠libresilicon.com 26 Oct '19

26 Oct '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, 27/10/2019, at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. Thanks for the attention!

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A new logic family with working devices in just 4 layer
by Pavel Nikulin 22 Oct '19

22 Oct '19

Hello David! A news passed by me today that there is a new logic family based on BJT + Zenner in which you can make working logic in just 4 layers https://www.eetimes.com/document.asp?doc_id=1335216 , and mixed signals in 8. Performance is claimed to be "CMOS-like" Quite remarkable, I think. Are you going with regular CMOS?

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A new logic family with working devices in just 4 layer
by Pavel Nikulin 22 Oct '19

22 Oct '19

Hello David! A news passed by me today that there is a new logic family based on BJT + Zenner in which you can make working logic in just 4 layers https://www.eetimes.com/document.asp?doc_id=1335216 , and mixed signals in 8. Performance is claimed to be "CMOS-like" Quite remarkable, I think. Are you going with regular CMOS?

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