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Status request: ADC
by David Lanzendörfer 03 Jan '19

03 Jan '19

Hi One of the new faces at the table started to draw together an ADC with Magic. What's the status there? Cheers David

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Libre RISCV SoC (CPU VPU GPU)
by Luke Kenneth Casson Leighton 03 Jan '19

03 Jan '19

Hi ok so a quick update, some fascinating discussion underway on comp.arch over the past month, in which various people including Mitch Alsup have been educating me about multi issue architectures and how to do precise exceptions, branch speculation, and much more, using scoreboards based on the PROPER understanding of a 58 year old supercomputer called the Cray CDC 6600. Updates are at https://www.crowdsupply.com/libre-risc-v/m-class slightly behind, I have 7 outstanding to be reviewed and published. The SoC is to be quad core dual issue for 64 bit and quad issue for 32 bit vectorised instructions, 8 issue for 16 and 8 bit vectors. Vectors are variable length and predicated, being dropped directly onto the multi issue queue, rather than being a fake SIMD knockoff. 3D instructions will be added as necessary, identified already is the conversion from FP ARGB to 32 bit ARGB pixels, these to be done as vectors, vectorisation taken care of by the multi-issue execution engine, just like for every other instruction. Target performance is 5-6 GFLOPs, 100 M pixels/sec (1280x720 @ 25fps), 30 M triangles/s, if we exceed that, whoopee. Power budget 2.5 watts total system. VPU target, 720p decode, again only accelerate with custom ops where needed. It is a fascinating and scary microarchitecture that subdivides the register file into 4 32 bit banks of 2R1W cells with individual byte-write-enable lines, passthrough write to read ports in same cycle, where the 4 banks are split odd-even and hi32 lo32. Hence why it is dual issue for 64 bit and quad for 32 bit. A separate additional bus exists for operand forwarding, even though the writethru capability of the regfile also provides a type of operand forwarding. This because FMAC requires 3R1W normally, and the extra forwarding bus, if the FMACs are chained (src of 1 is dest of previous) will allow 4 32 bit FMACs per clock per 800mhz core, for a total of 12GFLOPs, 2x the target performance. Without the extra bus performance is halved as the banks of only 2R1W regfile becomes the bottleneck. I wont go into detail on how the 16 and 8 bit ops are handled, its too scary :) took weeks to work out. Overall going well, could use some help, we picked nmigen because it results in readable flexible code, no nonsense with #ifdefs and we have too much that needs OO programming to mess about with #ifdefs in native verilog. L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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Small Update from 35c3
by Hagen SANKOWSKI 29 Dec '18

29 Dec '18

Hello List. Well, we are here at Leipzig, talking with many, many nerds, hackers, tinkerers and other lifeforms on the 35. Chaos Communication Congress (short 35c3). We gave our talk, which can be viewed here https://media.ccc.de/v/35c3-9410-libresilicon https://www.youtube.com/watch?v=DZq5Ryt3Wto and also w/ German translation https://www.youtube.com/watch?v=ABdpEcNekL0 What a overwhelming event! If you are at the 35c3 also, you can find us in the CCL building, just behind the tunnel from the entry hall, and the information desk there. Nice to see you personal! Regards, Hagen.

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Pinging Tim Edwards: Two questions
by Christoph Maier 28 Dec '18

28 Dec '18

Hi Mr. Potbox! [http://lcr.uns.edu.ar/electronica/vlsi/LabWork/lab00.pdf, http://people.biology.ucsd.edu/gert/pubs/iscas98_log.pdf] Been there, translated the talk, got the <expletive deleted> t-shirt. Are these guys real? How busy are you as the Principal Analog/Mixed Signal Designer of efabless? Curious minds want to know ... Christoph Maier ["officially", still affiliated with these guys, one of whom you may know: http://isn.ucsd.edu/people.html] [referring to:] R. Timothy Edwards rtedwards8 at gmail.com Thu Nov 22 22:01:57 CET 2018 Previous message: [Libre-silicon-devel] T-Shirt Next message: [Libre-silicon-devel] T-Shirt Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] ________________________________ Hello David, > For the 35c3 I've been designing the front of the T-Shirt > (Yes. I did it in magic) > What do you think about it? > https://github.com/libresilicon/PearlRiver/blob/master/Layout/img/tshirt.png I dare say it will be the first T-shirt ever to be designed in magic. . . ---Tim +--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: tim at opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+

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See You at 35c3 in Leipzig?
by Hagen SANKOWSKI 20 Dec '18

20 Dec '18

Hello List! Well, for the last weeks we were quite busy with our PearlRiver Wafer. So, I like to share the current status with you. We released the first Version of PearlRiver, gotten already the Masks. Thanks for the Sponsoring! David and Victor are currently manufacture Wafer by Wafer in NFF lab at HKUST on a daily base. In the same time we got the T-Shirts, marking the Release (as someone might noticed on this Mailing List). The T-Shirts will travel with David, Victor and Andi via Frankfurt/Main to Leipzig. And yes, our Talk about Libresilicon was accepted from the CCC Org-Team. We got 3 Speaker Tickets for the 35c3 and will be seen there on Scene https://fahrplan.events.ccc.de/congress/2018/Fahrplan/events/9410.html just on Day 1 - Dec. 27, 12:50h. If you are personaly on the Congress, please come to "Eliza". Or, if you like, look the life stream or later the recording via Internet. I hope, we can meet and great many of you on the Congress! https://events.ccc.de/congress/2018/wiki/index.php/Main_Page Hagen. -- "They who can give up essential liberty to obtain a little temporary safety, deserve neither liberty nor safety." Benjamin Franklin (1775)

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Packaging
by David Lanzendörfer 15 Dec '18

15 Dec '18

Hello list I've been approached by people on Twitter and they asked whether we could package our North Point and follow up MCUs as TQFN as well. Hagen asked me to collect a list of packages we should support for the MCUs: QFN and MLF are specified in JEDEC MO-220: * TQFN * QFN As described http://www.asekh.aseglobal.com/content/2-2-3.html The QFP packages (TQFP and LQFP) And of course dual inline packaging https://en.wikipedia.org/wiki/Dual_in-line_package Looking forward to your feedback David

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T-Shirt
by David Lanzendörfer 02 Dec '18

02 Dec '18

Hi folks For the 35c3 I've been designing the front of the T-Shirt (Yes. I did it in magic) What do you think about it? https://github.com/libresilicon/PearlRiver/blob/master/Layout/img/tshirt.png Cheers David

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F.Y.I. - get yourself prepared for designing a GPU
by Hagen SANKOWSKI 27 Nov '18

27 Nov '18

https://iq.opengenus.org/basic-graphics-processing-unit-gpu-design-concepts/ very simplistic

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turning verilog into graphical layout (PCB component style)
by Luke Kenneth Casson Leighton 27 Nov '18

27 Nov '18

hi, are there any tools that will take verilog and generate something akin to a PCB "component" plus show a set of "unrouted nets"? i would like to get a visual feel for what a design looks like, and a conversion of verilog to "blocks" is the easiest way i can think of. l.

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Mask placement
by David Lanzendörfer 26 Nov '18

26 Nov '18

Hi I've now placed the layers within the mask frame https://github.com/libresilicon/PearlRiver/tree/master/Vendors/HKUST/Masks Reduction factor is 5:1 so I scaled it up a bit. If it's ok with you, I will manufacture them together with the responsible guy, in the lab on Monday or so. Cheers David

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