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Contact pad mechanics
by David Lanzendörfer 22 Aug '18

22 Aug '18

Hi List, Hi Hagen Hagen and I had a discussion yesterday about the mechanics of our bonding pads and how physical stress when putting a probe onto the pad as well as bonding might impact the crystal. I've found this interesting IEEE approved paper on this topic[1]. Conlusion from this paper is: We can just make the top metal layer a big square and all the lower metal layers patterned with the cifoutput square expression. And it doesn't really matter with the frequencies as much as Hagen was afraid it would apparently, because they explicitly state these pattern shapes are also suitable for higher frequencies. One could even build the ESD circuit directly under the bonding pad and the chip would still perform. I'm looking forward to hearing from you, what you folks are thinking. Cheers David [1] http://www.ics.ee.nctu.edu.tw/~mdker/Referred%20Journal%20Papers/27tcapt03-…

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Update
by David Lanzendörfer 20 Aug '18

20 Aug '18

Hi all So I've now received my own clean room suit and it's now hanging there close to the air shower door at the entrance to the clean room. Also we found out today that there is still an issue with the RFID card, which might be caused by the fact that they haven't sent us the bill for the rent yet and so we haven't paid yet either... No cause for worrying though, because I've got the contract signed and the access card, it's most likely bureaucratic processes and so. Anyway. This Saturday I move into the new apartment and Hagen should be arriving here in Hong Kong and attend the orientation course and the exam soon after arrival, so that he can get his own user card for accessing the lab. We haven't gotten a clear date from Terry yet, because she's out of office until Wednesday. Also: I've now fixed up some of the stuff Tim suggested and introduced a poly resistor type (layer: resistor) in the scmos specs for Magic. This will be merged by cifoutput into the poly mask layer as well as into the silicide_stop layer in a 1 lambda bloated form. In it's written scmos8m.tech: layer CRG rp calma 67 0 But I wanna make sure that even with an alignment offset, the whole poly stripe is being covered by oxide, that's why I wanna bloat it by one lambda. Like: layer CRG rp grow lambda_1 calma 9 0 Anything speaking against it? Cheers David

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Clock generation
by David Lanzendörfer 20 Aug '18

20 Aug '18

Hi Hagen We could theoretically just use a Pierce oscillator, because you've already drawn the inverter circuit and could test this way, which one performs best to generate a square clock signal? What do you think? An idea for a test structure? https://en.wikipedia.org/wiki/Pierce_oscillator Cheers David

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Magic CIF output support for LibreSilicon
by David Lanzendörfer 19 Aug '18

19 Aug '18

Hi List, Hi Tim, Hi Hagen @Tim: I've added the specs for LibreSilicon in Magic: https://github.com/libresilicon/magic-8.2/commit/90ecfd589e0c05bc9a4dd5a274… Please review and give feedback @Hagen: I've changed the generator script accordingly to the new tech spec and changed the layer of the pad in the pad cells from "metal1" to "pad" Please review here: https://github.com/chipforge/PearlRiver/pull/3 Cheers David

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Mumble today, 9pm HKT
by David Lanzendörfer 19 Aug '18

19 Aug '18

Hi folks Don't forget the mumble session tonight at 9pm HKT We've got also a video streaming capable video conferencing tool ready now on https://meet.lanceville.hk/libresilicon Which we could start to a stream with on Youtube if it turns out that we have some neat stuff to show with screen sharing :-) Cheers David

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Netlist and LVS for PearlRiver
by Staf Verhaegen 10 Aug '18

10 Aug '18

Hello, I had a quick look at the current PearlRiver design(s). I also see layout not schematics or netlists. Do you plan to simulatie your measurement procedures before actually manufacturing the wafer ? Normal design procedure for analog (test) circuits is first do schematic capture, simulate the test procedure and then make layout according to schema and make it LVS (layout-versus-schematic) clean. Specifically for the L500_MOSFET_aligning structure which is indicated to also be used for measuring resistance and capacitance. To save pins I see a lot of pins are shared. For example I see that the middle pin is both connected to NWELL as to PSUB/PWELL which seems dangerous to me. In general I see that almost all of the pins are in one way connected to NWELL or PSUB/PWELL and basically shorted with other pins through these wells and also metal1. So I am wondering which resistances you actually try to measure here. greets, Staf.

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YouTube live streaming
by David Lanzendörfer 07 Aug '18

07 Aug '18

Hi Hagen, hi everyone I've now finally managed to get the recording and streaming working in our new Jitsi setup under https://meet.lanceville.hk I'd like to start streaming our engineering session and having screen sharing available also makes it easier to discuss things. Also when discussing serious problems it's better to see each others face in order to get a better idea on how they feel about something. I hope until next Sunday Hagen can fix his microphone setup so that we can try our first LibreSilicon engineering live stream on YouTube. Cheers David

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YouTube live streaming
by David Lanzendörfer 06 Aug '18

06 Aug '18

Hi Hagen, hi everyone I've now finally managed to get the recording and streaming working in our new Jitsi setup under https://meet.lanceville.hk I'd like to start streaming our engineering session and having screen sharing available also makes it easier to discuss things. Also when discussing serious problems it's better to see each others face in order to get a better idea on how they feel about something. I hope until next Sunday Hagen can fix his microphone setup so that we can try our first LibreSilicon engineering live stream on YouTube. Cheers David

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Youtube life streams
by David Lanzendörfer 03 Aug '18

03 Aug '18

Hi folks We've got a video conferencing tool now (Jitsi) on: https://meet.lanceville.hk It's kindof buggy under Chromium, but when using FireFox everything works. Do we wanna stream tandem-layouting on Youtube, so that folks can follow the design process? If yes: Might we wanna start this Sunday? Cheers David

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Access and mask set (MOSIS <-> LibreSilicon )
by David Lanzendörfer 03 Aug '18

03 Aug '18

Hi all, hi Hagen Today I've received the RFID card for the lab, which means I can go in there whenever I want now :-) Following things have come up so far: a) We need additional pwell in the cell layouts, because we need to lift the potential/doping of the p-substrate and I wanna keep the higher resistance in the non active areas. Also the process contains a step for building in pwells so that in case someone wants to use n-substrate or undoped substrate, they can just change the doping parameters. b) I've now figured out how to map the layers from MOSIS to GDS2 so that we can build it with our process. For instance ptransistor and ntransistor are both included in both masks: The poly-mask together with polysilicon as well as the pimplant mask/nimplant mask. Also we will have to include the pdcontact within the pimplant mask. @Hagen: Can you add pwells into the standard cells? Then we can actually just use MOSIS and merge the layers accordingly to our process. I'm now fixing up some details about our process, like the Aluminum and isolation oxide layer thicknesses and then we can generate GDS2 files from your layout, upload the GDS2 to the web interface, pay the mask set and get started in the lab. Cheers David

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