Hi I now went through all the machines we're going to use and there is nothing which keeps us from having a feature size from 0.5 um in overall. Which means that the smallest an inverter could get is 2.5 um x 8.0um Also if someone feels like figuring out how to render this document into HTML feel free. I think it slowly becomes too big of a document to ship it as a PDF... I'll drop some explenation on why the oxide etching with 0.5um isn't an issue as long as the mask is exposed properly in the document, but I think it's pretty clear, that there will be nothing stopping us from at least scaling down to 500nm pretty quickly as soon as we've got 1um working... At least from the lithographic and equipment point of view. Cheers David
Hello List, Hello David. On 03/12/2018 06:41 PM, David Lanzendörfer wrote:
I now went through all the machines we're going to use and there is nothing which keeps us from having a feature size from 0.5 um in overall. Which means that the smallest an inverter could get is 2.5 um x 8.0um Also if someone feels like figuring out how to render this document into HTML feel free. I think it slowly becomes too big of a document to ship it as a PDF...
I'll drop some explenation on why the oxide etching with 0.5um isn't an issue as long as the mask is exposed properly in the document, but I think it's pretty clear, that there will be nothing stopping us from at least scaling down to 500nm pretty quickly as soon as we've got 1um working... At least from the lithographic and equipment point of view.
Thanks again for your effort! Looks awesome - 3 technology nodes ahead. BTW, every next technology node is something like feature size of the node before divided by 2nd-root of two. This cut in half the area for the cell. I think, we need this 1 um anyway for chips working on 5 Volt. This is also quite suitable for analog stuff like op-amps. With 0.5 um only we are already in the 3.3 Volt domain, 5 Volt is to high for this small gates. The best trade-off between 5 and 3.3 Volt was the node between (0.7 .. 0.8 um) - with different transistor sizing both voltages can be applied. Currently I do not like to mix-up different voltages on the same chip - for instance by using 5 Volt at the IO-Ring and 3.3 Volt in the core area for all standard cells. This challenge we get soon with lower voltages for core area while staying compatible with outside-the-chip world with higher voltages.
Hi So I'd say we for now indeed just do 1um and then just run a 500nm node on 3.3V only for SoCs and thelike. After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power supply anyway. But yeah, if 5V tolerance is required in 500nm technology we will have to use the l=1um transistors from the 1um technology within the l=500nm technology for the buffer transistors. Maybe we make "modular pad cells" which can be modified to provide 3V3 instead of 5V as well to the internal logic? Or maybe we just will have to modify our pad cells for the 500nm technology and require two power supplies, one for IO and one for internal circuitry? Or maybe have only one VDD and then a lot of linear voltage regulators built into the CMOS chips? Cheers David On Tuesday, 13 March 2018 5:44:56 PM HKT Hagen SANKOWSKI wrote:
Hello List, Hello David.
On 03/12/2018 06:41 PM, David Lanzendörfer wrote:
I now went through all the machines we're going to use and there is nothing which keeps us from having a feature size from 0.5 um in overall. Which means that the smallest an inverter could get is 2.5 um x 8.0um Also if someone feels like figuring out how to render this document into HTML feel free. I think it slowly becomes too big of a document to ship it as a PDF...
I'll drop some explenation on why the oxide etching with 0.5um isn't an issue as long as the mask is exposed properly in the document, but I think it's pretty clear, that there will be nothing stopping us from at least scaling down to 500nm pretty quickly as soon as we've got 1um working... At least from the lithographic and equipment point of view.
Thanks again for your effort!
Looks awesome - 3 technology nodes ahead. BTW, every next technology node is something like feature size of the node before divided by 2nd-root of two. This cut in half the area for the cell.
I think, we need this 1 um anyway for chips working on 5 Volt. This is also quite suitable for analog stuff like op-amps.
With 0.5 um only we are already in the 3.3 Volt domain, 5 Volt is to high for this small gates.
The best trade-off between 5 and 3.3 Volt was the node between (0.7 .. 0.8 um) - with different transistor sizing both voltages can be applied.
Currently I do not like to mix-up different voltages on the same chip - for instance by using 5 Volt at the IO-Ring and 3.3 Volt in the core area for all standard cells. This challenge we get soon with lower voltages for core area while staying compatible with outside-the-chip world with higher voltages.
-- Best regards CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen
On 03/13/2018 11:13 AM, David Lanzendörfer wrote:
Hi So I'd say we for now indeed just do 1um and then just run a 500nm node on 3.3V only for SoCs and thelike.
After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power supply anyway.
But yeah, if 5V tolerance is required in 500nm technology we will have to use the l=1um transistors from the 1um technology within the l=500nm technology for the buffer transistors.
Maybe we make "modular pad cells" which can be modified to provide 3V3 instead of 5V as well to the internal logic? Or maybe we just will have to modify our pad cells for the 500nm technology and require two power supplies, one for IO and one for internal circuitry? Or maybe have only one VDD and then a lot of linear voltage regulators built into the CMOS chips?
I'll think about that. Unified IO-Cells should not be an issue as - transistor sizes in Pad-Cells only depends on current they have to drive outside and the ESD protection diodes; - there limitation in size is and will be the pad size with approx. 90..100um by 90..100um itself. This is decoupled from our feature size. So, we can design IO-Pad-Cells with unified size, which applicable on all our technology nodes. In the end, the layouter will choose the Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even lower cells. Voltage regulators are quite ugly while taking a lot of area and spreading heat into the die. And, we do not have transformers on die.
One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 V iirc. Having external current limit resistors at the pins exposed to 5v and internal diodes at the io pins against gnd and vcc to carry away the current this could work. xilinx does so with some fpgas with application notes that one can use them for 5v io. But be warned, if there is current creeping in from the IO-Ring to the VDD of the chip, the IO-Voltage ring needs to be limited in voltage as the current rushing in can lift up the 3,3V rail, so one needs an external transzorb diode to eat up the exxesive voltage. On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de> wrote:
On 03/13/2018 11:13 AM, David Lanzendörfer wrote:
Hi So I'd say we for now indeed just do 1um and then just run a 500nm node on 3.3V only for SoCs and thelike.
After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power supply anyway.
But yeah, if 5V tolerance is required in 500nm technology we will have to use the l=1um transistors from the 1um technology within the l=500nm technology for the buffer transistors.
Maybe we make "modular pad cells" which can be modified to provide 3V3 instead of 5V as well to the internal logic? Or maybe we just will have to modify our pad cells for the 500nm technology and require two power supplies, one for IO and one for internal circuitry? Or maybe have only one VDD and then a lot of linear voltage regulators built into the CMOS chips?
I'll think about that.
Unified IO-Cells should not be an issue as - transistor sizes in Pad-Cells only depends on current they have to drive outside and the ESD protection diodes; - there limitation in size is and will be the pad size with approx. 90..100um by 90..100um itself.
This is decoupled from our feature size. So, we can design IO-Pad-Cells with unified size, which applicable on all our technology nodes. In the end, the layouter will choose the Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even lower cells.
Voltage regulators are quite ugly while taking a lot of area and spreading heat into the die. And, we do not have transformers on die.
_______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
IMHO the best way is to have for 1 um - 5 Volt VDD pads - IO-Cells which working with 5 Volt - and of course such Standard Cells => this give us all the stuff for Maker, Tinker, Geeks which dealing with 5 Volt Circuits for 0.8 um - 3.3 Volt VDD pads, as well as 5 Volt VDD pads - two Standard Cell Libraries, one for 5 V core Voltage, another for 3.3 core Voltage => this is a little bit hybrid, someone can use the technology for 5 Volt or for 3.3 Volt supply for 0.5 um - 3.3 Volt VDD pads - IO-Cells which working with 3.3 Volt only - Standard Cells for 3.3 Volt only => most circuits now can deal with 3.3 Volt also below 0.5 um - different VDD Supply pads - different IO-Pad Cells for different power supplies - Standard Cells at lowest Voltage which is acceptable - Level Shifter between core area and Pad Cells => this becomes a mess Here we should, at the least, think about differential IO-Pads, with 100..150mV swing. The Voltage steps I am aware of are - 5 Volt - 3.3 Volt - 2.5 Volt - 1.8 Volt - 1.5 Volt - 1.25 Volt - 1 Volt The smallest feasible core Voltage seems to be 0.95 Volt. Otherwise the trade-off between reducing the threshold voltages, the number of stacked transistors which is still possible and the noise margin between low and high levels will bite us in the ass. On 03/13/2018 11:45 AM, ludwig jaffe wrote:
One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 V iirc. Having external current limit resistors at the pins exposed to 5v and internal diodes at the io pins against gnd and vcc to carry away the current this could work. xilinx does so with some fpgas with application notes that one can use them for 5v io. But be warned, if there is current creeping in from the IO-Ring to the VDD of the chip, the IO-Voltage ring needs to be limited in voltage as the current rushing in can lift up the 3,3V rail, so one needs an external transzorb diode to eat up the exxesive voltage.
On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de <mailto:hsank@posteo.de>> wrote:
On 03/13/2018 11:13 AM, David Lanzendörfer wrote: > Hi > So I'd say we for now indeed just do 1um and then just run a 500nm node on > 3.3V only for SoCs and thelike. > > After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power > supply anyway. > > But yeah, if 5V tolerance is required in 500nm technology we will have to use > the l=1um transistors from the 1um technology within the l=500nm technology > for the buffer transistors. > > Maybe we make "modular pad cells" which can be modified to provide 3V3 instead > of 5V as well to the internal logic? > Or maybe we just will have to modify our pad cells for the 500nm technology > and require two power supplies, one for IO and one for internal circuitry? > Or maybe have only one VDD and then a lot of linear voltage regulators built > into the CMOS chips?
I'll think about that.
Unified IO-Cells should not be an issue as - transistor sizes in Pad-Cells only depends on current they have to drive outside and the ESD protection diodes; - there limitation in size is and will be the pad size with approx. 90..100um by 90..100um itself.
This is decoupled from our feature size. So, we can design IO-Pad-Cells with unified size, which applicable on all our technology nodes. In the end, the layouter will choose the Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even lower cells.
Voltage regulators are quite ugly while taking a lot of area and spreading heat into the die. And, we do not have transformers on die.
_______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@list.libresilicon.com> http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel>
This Idea of Hagen is very good but remember that one needs diods to protect the different voltage rails against each other. These Diodes may be external but one needs to write it into the datasheets that they are needed, otherwhise the device could break. On Tue, Mar 13, 2018 at 7:08 AM, Hagen SANKOWSKI <hsank@posteo.de> wrote:
IMHO the best way is to have
for 1 um - 5 Volt VDD pads - IO-Cells which working with 5 Volt - and of course such Standard Cells
=> this give us all the stuff for Maker, Tinker, Geeks which dealing with 5 Volt Circuits
for 0.8 um - 3.3 Volt VDD pads, as well as 5 Volt VDD pads - two Standard Cell Libraries, one for 5 V core Voltage, another for 3.3 core Voltage
=> this is a little bit hybrid, someone can use the technology for 5 Volt or for 3.3 Volt supply
for 0.5 um - 3.3 Volt VDD pads - IO-Cells which working with 3.3 Volt only - Standard Cells for 3.3 Volt only
=> most circuits now can deal with 3.3 Volt also
below 0.5 um - different VDD Supply pads - different IO-Pad Cells for different power supplies - Standard Cells at lowest Voltage which is acceptable - Level Shifter between core area and Pad Cells
=> this becomes a mess Here we should, at the least, think about differential IO-Pads, with 100..150mV swing.
The Voltage steps I am aware of are - 5 Volt - 3.3 Volt - 2.5 Volt - 1.8 Volt - 1.5 Volt - 1.25 Volt - 1 Volt The smallest feasible core Voltage seems to be 0.95 Volt. Otherwise the trade-off between reducing the threshold voltages, the number of stacked transistors which is still possible and the noise margin between low and high levels will bite us in the ass.
On 03/13/2018 11:45 AM, ludwig jaffe wrote:
One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 V iirc. Having external current limit resistors at the pins exposed to 5v and internal diodes at the io pins against gnd and vcc to carry away the current this could work. xilinx does so with some fpgas with application notes that one can use them for 5v io. But be warned, if there is current creeping in from the IO-Ring to the VDD of the chip, the IO-Voltage ring needs to be limited in voltage as the current rushing in can lift up the 3,3V rail, so one needs an external transzorb diode to eat up the exxesive voltage.
On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de <mailto:hsank@posteo.de>> wrote:
On 03/13/2018 11:13 AM, David Lanzendörfer wrote: > Hi > So I'd say we for now indeed just do 1um and then just run a 500nm node on > 3.3V only for SoCs and thelike. > > After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power > supply anyway. > > But yeah, if 5V tolerance is required in 500nm technology we will have to use > the l=1um transistors from the 1um technology within the l=500nm technology > for the buffer transistors. > > Maybe we make "modular pad cells" which can be modified to provide 3V3 instead > of 5V as well to the internal logic? > Or maybe we just will have to modify our pad cells for the 500nm technology > and require two power supplies, one for IO and one for internal circuitry? > Or maybe have only one VDD and then a lot of linear voltage regulators built > into the CMOS chips?
I'll think about that.
Unified IO-Cells should not be an issue as - transistor sizes in Pad-Cells only depends on current they have to drive outside and the ESD protection diodes; - there limitation in size is and will be the pad size with approx. 90..100um by 90..100um itself.
This is decoupled from our feature size. So, we can design IO-Pad-Cells with unified size, which applicable on all our technology nodes. In the end, the layouter will choose the Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even lower cells.
Voltage regulators are quite ugly while taking a lot of area and spreading heat into the die. And, we do not have transformers on die.
_______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@ list.libresilicon.com> http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel>
If possible I'd like to include the diodes within the layout. I'm right now defining multiple test cases for multiple different diode cases in the process doc. Maybe you can look over it and add categories if you like. We have to define a the layout for the test wafer now... Cheers David On Tuesday, 13 March 2018 7:39:22 PM HKT ludwig jaffe wrote:
This Idea of Hagen is very good but remember that one needs diods to protect the different voltage rails against each other. These Diodes may be external but one needs to write it into the datasheets that they are needed, otherwhise the device could break.
On Tue, Mar 13, 2018 at 7:08 AM, Hagen SANKOWSKI <hsank@posteo.de> wrote:
IMHO the best way is to have
for 1 um - 5 Volt VDD pads - IO-Cells which working with 5 Volt - and of course such Standard Cells
=> this give us all the stuff for Maker, Tinker, Geeks which dealing with 5 Volt Circuits
for 0.8 um - 3.3 Volt VDD pads, as well as 5 Volt VDD pads - two Standard Cell Libraries, one for 5 V core Voltage, another for 3.3 core Voltage
=> this is a little bit hybrid, someone can use the technology for 5 Volt or for 3.3 Volt supply
for 0.5 um - 3.3 Volt VDD pads - IO-Cells which working with 3.3 Volt only - Standard Cells for 3.3 Volt only
=> most circuits now can deal with 3.3 Volt also
below 0.5 um - different VDD Supply pads - different IO-Pad Cells for different power supplies - Standard Cells at lowest Voltage which is acceptable - Level Shifter between core area and Pad Cells
=> this becomes a mess Here we should, at the least, think about differential IO-Pads, with 100..150mV swing.
The Voltage steps I am aware of are - 5 Volt - 3.3 Volt - 2.5 Volt - 1.8 Volt - 1.5 Volt - 1.25 Volt - 1 Volt The smallest feasible core Voltage seems to be 0.95 Volt. Otherwise the trade-off between reducing the threshold voltages, the number of stacked transistors which is still possible and the noise margin between low and high levels will bite us in the ass.
On 03/13/2018 11:45 AM, ludwig jaffe wrote:
One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 V
iirc.
Having external current limit resistors at the pins exposed to 5v and internal diodes at the io pins against gnd and vcc to carry away the current this could
work.
xilinx does so with some fpgas with application notes that one can use them for 5v io. But be warned, if there is current creeping in from the IO-Ring to the VDD of the chip, the IO-Voltage ring needs to be limited in voltage as the current rushing in can lift up the 3,3V rail, so one needs an external transzorb diode to eat up the exxesive voltage.
On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de
<mailto:hsank@posteo.de>> wrote: On 03/13/2018 11:13 AM, David Lanzendörfer wrote: > Hi > So I'd say we for now indeed just do 1um and then just run a 500nm
node on
> 3.3V only for SoCs and thelike. > > After all, these SoCs and CPUs usually get a 3V3 rail from the ATX
power
> supply anyway. > > But yeah, if 5V tolerance is required in 500nm technology we will
have to use
> the l=1um transistors from the 1um technology within the l=500nm
technology
> for the buffer transistors. > > Maybe we make "modular pad cells" which can be modified to provide
3V3 instead
> of 5V as well to the internal logic? > Or maybe we just will have to modify our pad cells for the 500nm
technology
> and require two power supplies, one for IO and one for internal
circuitry?
> Or maybe have only one VDD and then a lot of linear voltage
regulators built
> into the CMOS chips?
I'll think about that.
Unified IO-Cells should not be an issue as - transistor sizes in Pad-Cells only depends on current they have to drive outside and the ESD protection diodes; - there limitation in size is and will be the pad size with approx. 90..100um by 90..100um itself.
This is decoupled from our feature size. So, we can design IO-Pad-Cells with unified size, which applicable on all our technology nodes. In the end, the layouter will choose the Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even
lower
cells.
Voltage regulators are quite ugly while taking a lot of area and spreading heat into the die. And, we do not have transformers on die.
_______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@
list.libresilicon.com>
http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel>
-- Best regards CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen
Hello. Well, on the test wafer die we have to verify our diode design. As long as we do not mixing-up different Supply Voltage Levels, this diodes are not needed between the rails. We need indeed diodes for the ESD protection, which are quite large also. Thinking about my last Email I am not sure anymore, why we should pick-up the doubled effort to design two libraries with different voltage levels for the 0.8 um node.. I guess, we could be fine with 1 um for 5 Volt and 0.5 um for 3.3 Volt and drop the 0.8 um beside.. Missing this node we step faster from 1 um down to 0.5 um and open the hell later below 500 nm. I guess also, we currently do not haven the working power to make a lot of faculty stuff. Any other objections? On 03/13/2018 12:39 PM, ludwig jaffe wrote:
This Idea of Hagen is very good but remember that one needs diods to protect the different voltage rails against each other. These Diodes may be external but one needs to write it into the datasheets that they are needed, otherwhise the device could break.
On Tue, Mar 13, 2018 at 7:08 AM, Hagen SANKOWSKI <hsank@posteo.de <mailto:hsank@posteo.de>> wrote:
IMHO the best way is to have
for 1 um - 5 Volt VDD pads - IO-Cells which working with 5 Volt - and of course such Standard Cells
=> this give us all the stuff for Maker, Tinker, Geeks which dealing with 5 Volt Circuits
for 0.8 um - 3.3 Volt VDD pads, as well as 5 Volt VDD pads - two Standard Cell Libraries, one for 5 V core Voltage, another for 3.3 core Voltage
=> this is a little bit hybrid, someone can use the technology for 5 Volt or for 3.3 Volt supply
for 0.5 um - 3.3 Volt VDD pads - IO-Cells which working with 3.3 Volt only - Standard Cells for 3.3 Volt only
=> most circuits now can deal with 3.3 Volt also
below 0.5 um - different VDD Supply pads - different IO-Pad Cells for different power supplies - Standard Cells at lowest Voltage which is acceptable - Level Shifter between core area and Pad Cells
=> this becomes a mess Here we should, at the least, think about differential IO-Pads, with 100..150mV swing.
The Voltage steps I am aware of are - 5 Volt - 3.3 Volt - 2.5 Volt - 1.8 Volt - 1.5 Volt - 1.25 Volt - 1 Volt The smallest feasible core Voltage seems to be 0.95 Volt. Otherwise the trade-off between reducing the threshold voltages, the number of stacked transistors which is still possible and the noise margin between low and high levels will bite us in the ass.
On 03/13/2018 11:45 AM, ludwig jaffe wrote: > One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 V iirc. > Having external current limit resistors at the pins exposed to 5v and > internal diodes at > the io pins against gnd and vcc to carry away the current this could work. > xilinx does so with some fpgas with application notes that one can use > them for > 5v io. > But be warned, if there is current creeping in from the IO-Ring to the > VDD of the chip, > the IO-Voltage ring needs to be limited in voltage as the current > rushing in can lift up the > 3,3V rail, so one needs an external transzorb diode to eat up the > exxesive voltage. > > > On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de <mailto:hsank@posteo.de> > <mailto:hsank@posteo.de <mailto:hsank@posteo.de>>> wrote: > > > > On 03/13/2018 11:13 AM, David Lanzendörfer wrote: > > Hi > > So I'd say we for now indeed just do 1um and then just run a 500nm node on > > 3.3V only for SoCs and thelike. > > > > After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power > > supply anyway. > > > > But yeah, if 5V tolerance is required in 500nm technology we will have to use > > the l=1um transistors from the 1um technology within the l=500nm technology > > for the buffer transistors. > > > > Maybe we make "modular pad cells" which can be modified to provide 3V3 instead > > of 5V as well to the internal logic? > > Or maybe we just will have to modify our pad cells for the 500nm technology > > and require two power supplies, one for IO and one for internal circuitry? > > Or maybe have only one VDD and then a lot of linear voltage regulators built > > into the CMOS chips? > > I'll think about that. > > Unified IO-Cells should not be an issue as > - transistor sizes in Pad-Cells only depends on current they have to > drive outside and the ESD protection diodes; > - there limitation in size is and will be the pad size with approx. > 90..100um by 90..100um itself. > > This is decoupled from our feature size. > So, we can design IO-Pad-Cells with unified size, which applicable on > all our technology nodes. In the end, the layouter will choose the > Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even lower > cells. > > Voltage regulators are quite ugly while taking a lot of area and > spreading heat into the die. And, we do not have transformers on die. > > > _______________________________________________ > Libre-silicon-devel mailing list > Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@list.libresilicon.com> <mailto:Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@list.libresilicon.com>> > http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel> > <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel>> > >
Hi Hagen We could just use guard rings around each of the logic cells, which will guarantee us ESD protection on the whole logic. And yeah, I'd say we can just get 1um working, then jump to 500nm and start tinkering with SoCs and your FPGA! ;-) Cheers David On Tuesday, 13 March 2018 10:38:25 PM HKT Hagen SANKOWSKI wrote:
Hello.
Well, on the test wafer die we have to verify our diode design. As long as we do not mixing-up different Supply Voltage Levels, this diodes are not needed between the rails. We need indeed diodes for the ESD protection, which are quite large also.
Thinking about my last Email I am not sure anymore, why we should pick-up the doubled effort to design two libraries with different voltage levels for the 0.8 um node..
I guess, we could be fine with 1 um for 5 Volt and 0.5 um for 3.3 Volt and drop the 0.8 um beside.. Missing this node we step faster from 1 um down to 0.5 um and open the hell later below 500 nm. I guess also, we currently do not haven the working power to make a lot of faculty stuff.
Any other objections?
On 03/13/2018 12:39 PM, ludwig jaffe wrote:
This Idea of Hagen is very good but remember that one needs diods to protect the different voltage rails against each other. These Diodes may be external but one needs to write it into the datasheets that they are needed, otherwhise the device could break.
On Tue, Mar 13, 2018 at 7:08 AM, Hagen SANKOWSKI <hsank@posteo.de
<mailto:hsank@posteo.de>> wrote: IMHO the best way is to have
for 1 um - 5 Volt VDD pads - IO-Cells which working with 5 Volt - and of course such Standard Cells
=> this give us all the stuff for Maker, Tinker, Geeks which dealing with 5 Volt Circuits
for 0.8 um - 3.3 Volt VDD pads, as well as 5 Volt VDD pads - two Standard Cell Libraries, one for 5 V core Voltage, another for 3.3 core Voltage
=> this is a little bit hybrid, someone can use the technology for 5 Volt or for 3.3 Volt supply
for 0.5 um - 3.3 Volt VDD pads - IO-Cells which working with 3.3 Volt only - Standard Cells for 3.3 Volt only
=> most circuits now can deal with 3.3 Volt also
below 0.5 um - different VDD Supply pads - different IO-Pad Cells for different power supplies - Standard Cells at lowest Voltage which is acceptable - Level Shifter between core area and Pad Cells
=> this becomes a mess Here we should, at the least, think about differential IO-Pads, with 100..150mV swing.
The Voltage steps I am aware of are - 5 Volt - 3.3 Volt - 2.5 Volt - 1.8 Volt - 1.5 Volt - 1.25 Volt - 1 Volt The smallest feasible core Voltage seems to be 0.95 Volt. Otherwise the trade-off between reducing the threshold voltages, the number of stacked transistors which is still possible and the noise margin between low and high levels will bite us in the ass.
On 03/13/2018 11:45 AM, ludwig jaffe wrote: > One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 V > iirc. > Having external current limit resistors at the pins exposed to 5v > and > internal diodes at > the io pins against gnd and vcc to carry away the current this could > work. > xilinx does so with some fpgas with application notes that one can > use > them for > 5v io. > But be warned, if there is current creeping in from the IO-Ring to > the > VDD of the chip, > the IO-Voltage ring needs to be limited in voltage as the current > rushing in can lift up the > 3,3V rail, so one needs an external transzorb diode to eat up the > exxesive voltage. > > > On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de > <mailto:hsank@posteo.de>> > > <mailto:hsank@posteo.de <mailto:hsank@posteo.de>>> wrote: > On 03/13/2018 11:13 AM, David Lanzendörfer wrote: > > Hi > > So I'd say we for now indeed just do 1um and then just run a
500nm node on
> > 3.3V only for SoCs and thelike. > > > > After all, these SoCs and CPUs usually get a 3V3 rail from
the ATX power
> > supply anyway. > > > > But yeah, if 5V tolerance is required in 500nm technology we
will have to use
> > the l=1um transistors from the 1um technology within the
l=500nm technology
> > for the buffer transistors. > > > > Maybe we make "modular pad cells" which can be modified to
provide 3V3 instead
> > of 5V as well to the internal logic? > > Or maybe we just will have to modify our pad cells for the
500nm technology
> > and require two power supplies, one for IO and one for
internal circuitry?
> > Or maybe have only one VDD and then a lot of linear voltage
regulators built
> > into the CMOS chips? > > I'll think about that. > > Unified IO-Cells should not be an issue as > - transistor sizes in Pad-Cells only depends on current they
have to
> drive outside and the ESD protection diodes; > - there limitation in size is and will be the pad size with
approx.
> 90..100um by 90..100um itself. > > This is decoupled from our feature size. > So, we can design IO-Pad-Cells with unified size, which
applicable on
> all our technology nodes. In the end, the layouter will choose >the > Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or
even lower
> cells. > > Voltage regulators are quite ugly while taking a lot of area and > spreading heat into the die. And, we do not have transformers
on die.
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Below 500nm we will have to do "trickery" with multiple overlapping masks in order to get the smaller feature sizes going. The mask sets will become pretty expensive. We will have to manufacture and sell some of the 1um prototype and earn cash with selling these devices, then we can pay this expensive research ^^ Cheers David On Tuesday, 13 March 2018 11:08:36 PM HKT David Lanzendörfer wrote:
Hi Hagen We could just use guard rings around each of the logic cells, which will guarantee us ESD protection on the whole logic.
And yeah, I'd say we can just get 1um working, then jump to 500nm and start tinkering with SoCs and your FPGA! ;-)
Cheers David
On Tuesday, 13 March 2018 10:38:25 PM HKT Hagen SANKOWSKI wrote:
Hello.
Well, on the test wafer die we have to verify our diode design. As long as we do not mixing-up different Supply Voltage Levels, this diodes are not needed between the rails. We need indeed diodes for the ESD protection, which are quite large also.
Thinking about my last Email I am not sure anymore, why we should pick-up the doubled effort to design two libraries with different voltage levels for the 0.8 um node..
I guess, we could be fine with 1 um for 5 Volt and 0.5 um for 3.3 Volt and drop the 0.8 um beside.. Missing this node we step faster from 1 um down to 0.5 um and open the hell later below 500 nm. I guess also, we currently do not haven the working power to make a lot of faculty stuff.
Any other objections?
On 03/13/2018 12:39 PM, ludwig jaffe wrote:
This Idea of Hagen is very good but remember that one needs diods to protect the different voltage rails against each other. These Diodes may be external but one needs to write it into the datasheets that they are needed, otherwhise the device could break.
On Tue, Mar 13, 2018 at 7:08 AM, Hagen SANKOWSKI <hsank@posteo.de
<mailto:hsank@posteo.de>> wrote: IMHO the best way is to have
for 1 um - 5 Volt VDD pads - IO-Cells which working with 5 Volt - and of course such Standard Cells
=> this give us all the stuff for Maker, Tinker, Geeks which dealing with 5 Volt Circuits
for 0.8 um - 3.3 Volt VDD pads, as well as 5 Volt VDD pads - two Standard Cell Libraries, one for 5 V core Voltage, another for 3.3 core Voltage
=> this is a little bit hybrid, someone can use the technology for 5 Volt or for 3.3 Volt supply
for 0.5 um - 3.3 Volt VDD pads - IO-Cells which working with 3.3 Volt only - Standard Cells for 3.3 Volt only
=> most circuits now can deal with 3.3 Volt also
below 0.5 um - different VDD Supply pads - different IO-Pad Cells for different power supplies - Standard Cells at lowest Voltage which is acceptable - Level Shifter between core area and Pad Cells
=> this becomes a mess Here we should, at the least, think about differential IO-Pads, with 100..150mV swing.
The Voltage steps I am aware of are - 5 Volt - 3.3 Volt - 2.5 Volt - 1.8 Volt - 1.5 Volt - 1.25 Volt - 1 Volt The smallest feasible core Voltage seems to be 0.95 Volt. Otherwise the trade-off between reducing the threshold voltages, the number of stacked transistors which is still possible and the noise margin between low and high levels will bite us in the ass.
On 03/13/2018 11:45 AM, ludwig jaffe wrote: > One can have "5V-tolerable" 3,6V IO-Cells as TTLs High is only 3,6 > V > iirc. > Having external current limit resistors at the pins exposed to 5v > and > internal diodes at > the io pins against gnd and vcc to carry away the current this > could > work. > xilinx does so with some fpgas with application notes that one can > use > them for > 5v io. > But be warned, if there is current creeping in from the IO-Ring to > the > VDD of the chip, > the IO-Voltage ring needs to be limited in voltage as the current > rushing in can lift up the > 3,3V rail, so one needs an external transzorb diode to eat up the > exxesive voltage. > > > On Tue, Mar 13, 2018 at 6:36 AM, Hagen SANKOWSKI <hsank@posteo.de > <mailto:hsank@posteo.de>> > > > <mailto:hsank@posteo.de <mailto:hsank@posteo.de>>> wrote: > On 03/13/2018 11:13 AM, David Lanzendörfer wrote: > > Hi > > So I'd say we for now indeed just do 1um and then just run a
500nm node on
> > 3.3V only for SoCs and thelike. > > > > After all, these SoCs and CPUs usually get a 3V3 rail from
the ATX power
> > supply anyway. > > > > But yeah, if 5V tolerance is required in 500nm technology we
will have to use
> > the l=1um transistors from the 1um technology within the
l=500nm technology
> > for the buffer transistors. > > > > Maybe we make "modular pad cells" which can be modified to
provide 3V3 instead
> > of 5V as well to the internal logic? > > Or maybe we just will have to modify our pad cells for the
500nm technology
> > and require two power supplies, one for IO and one for
internal circuitry?
> > Or maybe have only one VDD and then a lot of linear voltage
regulators built
> > into the CMOS chips? > > I'll think about that. > > Unified IO-Cells should not be an issue as > - transistor sizes in Pad-Cells only depends on current they
have to
> drive outside and the ESD protection diodes; > - there limitation in size is and will be the pad size with
approx.
> 90..100um by 90..100um itself. > > This is decoupled from our feature size. > So, we can design IO-Pad-Cells with unified size, which
applicable on
> all our technology nodes. In the end, the layouter will choose > >the > > Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or
even lower
> cells. > > Voltage regulators are quite ugly while taking a lot of area > and > spreading heat into the die. And, we do not have transformers
on die.
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Hi, 0,5 and 1,0 would be valid steps. So starting with 5V at 1,0 structure would be valid. With 0,5 structure, I would suggest to have some thing "5V-tolerant with some hooks" like xilinx sells their older fpgas, as I described before, as it is nice to be able to interface with some lines of 5V level.
Hagen SANKOWSKI schreef op di 13-03-2018 om 10:44 [+0100]:
With 0.5 um only we are already in the 3.3 Volt domain, 5 Volt is to
high for this small gates.
I am using 0.35um TSMC here with 3.3V core and 5V IO. The minimum L for the 3.3V NMOS & PMOS is 0.35um and 0.5um for the 5V NMOS & PMOS. greets, Staf.
participants (4)
-
David Lanzendörfer -
Hagen SANKOWSKI -
ludwig jaffe -
Staf Verhaegen