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Reminder - next Mumble Session on June 3, 2018 21.00 HKT
by Hagen SANKOWSKI 13 Jun '18

13 Jun '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, June 3 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - test wafer structures - other stuff around libre silicon Happy to hear from you! Hagen

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Re: [Libre-silicon-devel] Which keywords are allowed as identifiers?/ Header files, geometry lib (boost geometry?) (#2)
by Paul 12 Jun '18

12 Jun '18

Hej David! > Unfortunately LEF is anything else than elegant. > That's why we wanna switch to ALF. > The grammar has grown historically over the year and Cadence defined > LEF/DEF > on a need-to-have basis and everyone uses it because there is nothing > better. > I unfortunately can't give any additional input on the topic of > parsing LEF > files other than there is a reason that my original grammar looked as > ugly as > it did. I agree, but doesn't mean, that we should drop support for LEFDEF, since there is already a lot of infrastructure for it, and since ALF is some kind of a LEFDEF superset, working on the subset contributes for both standards, so seems like almost free lunch for me :) > If you wanna have something elegant maybe really focus on ALF, so that > we can > provide our IP libs in that format instead. And since there are as much as zero ALF examples, we have to generate them ourself, and for me it sounds the best to convert them from the tones of LEFDEF out there... Another question. For the datastructures I would have boost geometry on my radar for all the polygon and rect stuff, since its the only lib I have experience with and I dont want to write myself all the polygon90 and geometry stuff. Any opinion about using boost geometry, alternative canidates for that or other geometry related stuff already used in the QTflow repo which I maybe don't know about :? Cheers! Paul

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Hackathon in Hong Kong at the 23th June
by David Lanzendörfer 11 Jun '18

11 Jun '18

Hi all Please find the information below for the Hackathon in Hong Kong: https://www.eventbrite.hk/e/g0vhkio-hackathon-tickets-45732122008 Please come and help developing QtFlow or maybe discuss the process draft we've got so far? Cheers David

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Wikibooks.org
by Hagen SANKOWSKI 02 Jun '18

02 Jun '18

Hello List! For everyone who is willing to learn more about the chip design flow - there is already a wikibook available https://en.wikibooks.org/wiki/Chip_Design_Made_Easy Happy Reading! Hagen Sankowski

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Clean room visit photos
by David Lanzendörfer 01 Jun '18

01 Jun '18

Hi everyone Here is a gallery with all the photos we've taken at the clean room at HKUST today: https://photos.app.goo.gl/zxsVn41fz9fPZAUv2 Enjoy! ^^ Cheers David

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Process flow generator
by David Lanzendörfer 30 May '18

30 May '18

Hi I'm right now working on a process flow generator which generates LaTeX and from there a PDF out of a YAML file in which the process is nicely written down. The key is here that you can add requirements for preparation steps between machines and it automatically checks for contamination control violations. What do you think? Might that be useful for anyone else except us? For us it will be very useful, because we won't make mistakes when planning processes anymore, at least on the contamination level. Cheers David

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RAM for LibreSilicon
by Hagen SANKOWSKI 30 May '18

30 May '18

Hello List! Today I came across this nice RAM Generator: https://github.com/VLSIDA/OpenRAM Usually, all the Memories on the Die are generated. This means, a Vendor provides a Script to generate the memory-structure with address decoders, storage cells, output buffers, build-in tests etc. Well, such a script I found on Github, and it is in Python. If it is working, or at least we could adapt it to provide sufficient memories, I am fine with that. In a good Borg-manner, we should assimilate OpenRAM into QtFlow. This scripts would helps a lot to design the first Microcontroller. Sometimes I really like github.com :-) Regards, Hagen.

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Re: [Libre-silicon-devel] STA and Simulation in a workflow
by Hagen SANKOWSKI 29 May '18

29 May '18

Hello Andreas. On 05/29/2018 04:34 PM, Andreas Westerwick wrote: > Hello List, > > this question comes in two parts and is for hardware designers: > > In the Alliance CAD System there is a tool called `asimut`, which does > VHDL simulation and is executed after each step in the workflow > basically. I do not see the reason for doing the simulation *after* *each* step in the workflow. Before getting the netlist, you do intensiv simulations for verifying your design. Afterwards, with place and route already done, the STA checks, that your design still meets the timing requirements. As Tim mentioned, you probably could verify that your design is still sane after place and route - with self-checking testbenches. Seriously, only a minority of designers can write good / sophisticated testbenches. So my guess here is, that the tool flow in Alliance misses something like a equivalence checking tool - before and after one processing step. That would be fine to have a EQ check. I am not sure, but I think I heard something in that direction from Clifford, that Yosys could do that. Let put us the Equivalence Check on the check-list for QtFlow. Because if their are processing steps, which could be risky, or you would still not trust the fresh developed tools - a EQ check can recognize whether the design is still logcial/functional the same as it was before the processing step. > Is there an equivalent simulation tool in `qflow` or is it comparable > to `ng-spice`? > Would you execute `ng-spice` after each step in a hardware design flow? Definitely not. And just for the record - analog simulations in spice (or ng-spice) are very time and memory consuming. Yoo wouldn't do them without a good reason. If we starting with digital design, pure digital simulations in Verilog e.g. with Icarus Verilog, are quite faster. Analog simulations I would start, if I like so-called Mixed-Signal-Simulation with analog-parts (e.g. a ADC, DAC, or PLL is involved) and digital control logic coupled to them. > The second question is about finding an equivalent STA tool to `vesta`. > STA is performed after Placing and then again after Routing, is this correct? STA tools are checking, whether the design - from a perspective of timing - still reaches the timing requirements. While with placement there is not a trustworthy source of timing information, the STA becomes useful after the Routing step. With routing, the wires gets there delay. > I cannot find a similar tool in the Alliance CAD System but it is necessary > for a complete silicon flow. Me too. Hagen.

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STA and Simulation in a workflow
by Andreas Westerwick 29 May '18

29 May '18

Hello List, this question comes in two parts and is for hardware designers: In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow? The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow. Kind regards, Andreas Westerwick

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Status check: Test structures?
by David Lanzendörfer 29 May '18

29 May '18

Hi Hagen Any updates on the test structures already? Cheers David

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