- Libresilicon-developers - libresilicon.com

ARM starts campaign against RISC-V?
by Hagen SANKOWSKI 10 Jul '18

10 Jul '18

Hello list members, can you check this? Is this [0] really a campaign against RISC-V, started by ARM? Arguments are very strange. I can't believe it, get the hint from fefes well-known blog [1] Regards, Hagen [0] https://riscv-basics.com/ [1] http://blog.fefe.de/?ts=a5bda6b9 [german]

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Status update
by David Lanzendörfer 07 Jul '18

07 Jul '18

Hi Following status changes which are partially significant occurred, in a positive way: a) I've now passed the safety examination and should get my RFID access card to the clean room in a week or so. >From that point on, the only thing keeping us from running the tests is the lack of a finalized test wafer layout. However, since the mask set costs around 1kUSD we shouldn't rush now, because rushing causes mistakes, and mistakes cost money. b) I've now worked myself into the topic of creating a generic DRAM controller out of lightdram, as Luke has suggested. Turns out it's a bunch of Python scripts which produce a single mashed together Verilog module. It's a total mess and ugly as hell. I think I will just "translate" this Python code into Scala/Chisel so that it can be used directly as an IP core in our SauMauPing framework. This will be especially relevant as soon as we switch over to the Yuen Long series which will be a full feature desktop CPU, which mins we will have DIMM/ SODIMM slots soldered to a DDR3/DDR4 bus, connected to the CPU. So it's already good if we have a nicely parameterizable version of a DDR3/ DDR4 controller inside Chisel. @Manili: Wanna help with porting the lightram code from Python to Chisel? Cheers David

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GPU/SoC
by David Lanzendörfer 30 Jun '18

30 Jun '18

Hi I'm now so far that it fetches the setup instructions from the boot ROM. Next step is getting it to boot from the SD card image provided by the SD card behavioral model. When I get this to work, I can use dd to make a bootable SD card and the ROM loader is anyway hard wired. With the DRAM Luke has suggested I see a bright future again for our own 100% libre SoC. As soon as I've got something that works and have fixed all the bugs (which I'd be ashamed of to mirror for all eternity on GitHub ^^') I will push it. @Hagen: I still haven't heard back from HKUST BTW Cheers David

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SoC for GPU project
by David Lanzendörfer 29 Jun '18

29 Jun '18

Hi I've now started wiring a RISC-V CPU generated with Rocket-Chip into a top level: https://github.com/leviathanch/SauMauPing1 However, for some reason it doesn't start trying to fetch instructions. I'll investigate tomorrow, for now I expect it to rain cats and dogs tonight and tomorrow as much as my head hurts right now. I'll relax now and get back tomorrow with lots of coffee. Another important topic which came up when I tried to repurpose the memory controller from the North Point project: We will have to develop SRAM for our MCU or solder an external SRAM chip onto the board... like this one: https://github.com/freecores/zbt_sram_controller/blob/master/ZBTSRAM61NLP_N… Didn't we have a talk some while ago with one of the folks from OpenRAM? That's exactly their department. We should tell them to be ready to get started dimensioning SRAM cells, as soon as we've got the first workable results from PearlRiver. Cheers David PS: Turned spell checker off now ^^

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Re: [Libre-silicon-devel] SoC for GPU project
by Mohammad Amin Nili 27 Jun '18

27 Jun '18

Hi all, After some works with Luke, we managed to create a feature/criteria list of the GPU. So if your GPU IP Core could pass these requirements you’ll choose for the $250,000 USD sponsorship. It is possible that the list change during the time so stay-tuned. However the main requirements (performance, power consumption and license type) won’t change. Here is the link: http://libre-riscv.org/shakti/m_class/libre_3d_gpu/ <http://libre-riscv.org/shakti/m_class/libre_3d_gpu/> Best regards, Manili P.S. Luke please correct me if I’m missing something.

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Results from yesterdays Mumble meeting
by David Lanzendörfer 27 Jun '18

27 Jun '18

Hi all Here's the results from yesterdays Mumble conference: We've decided that we will provide a collection of different example process documentations for different sets of machines available. For instance there will be a guide which helps someone to set up the process with only a diffusion furnace and wet etcher. But there will also be another guide for setting the process up with an ion implanter and more advanced equipment. Also we've decided that we will try to apply for this sponsorship from an anonymous sponsor which promised 250kUSD to someone who might develop a truly free GPU. (IMHO: Since we're the only ones working on a free manufacturing process, we're basically the only ones who could be chosen for that sponsorship, if they really would care about the meaning of truly Libre) Anyway... Manili (Mohammad Amin) joined the devteam yesterday and will help with developing the GPU of which we will show a prototype hopefully soon to this anonymous sponsor. @Manili: What SD card controller should we be using for our test SoC? This one maybe? (I've already written a RISC-V-Wishbone converter a while ago for the North Point MCU, which we could use): https://github.com/mczerski/SD-card-controller https://opencores.org/project/sd_card_controller Cheers David

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Status report #ImpostorSyndromePrevention
by David Lanzendörfer 26 Jun '18

26 Jun '18

Hi So, I've now started providing multiple separate process step docs for different degrees of equipment setup: https://github.com/libresilicon/process/tree/master/process_steps Also I've managed to automatically generate a core with SPI and DRAM controller and have to further work on it tomorrow (as well as the process) in order to make it synthesizable in a stand-alone fashion on a die: https://github.com/libresilicon/SauMauPing1 Also I've updated the links on the website so that both new process docs can be found there. (Table follows) @Hagen: I didn't have time to further work on QtFlow... But didn't we get like 6 new developers anyway at the last Hackathon? Can't they... well... take care of that? I've got only so many parallel threads available in my head before the overheat protection kicks in and it shuts down and needs to be rebooted ;-) Cheers -lev

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KLayout and QtFlow
by David Lanzendörfer 24 Jun '18

24 Jun '18

Hi list I've been looking through KLayout and they have some stuff implemented in a much more performant fashion than I did. The question is: Do we wanna drag in their code into QtFlow or maybe integrate our stuff as plugin into KLayout? Please give feedback on that. Also please have a look on the process, which I think is plus-minus done so far and ready for testing: https://github.com/libresilicon/process/blob/master/process_steps/process_s… Please come into Mumble this Sunday 9pm HKT and give your feedback on the process! Thanks David

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Next Mumble Session on June 24, 2018, 21.00 HKT
by David Lanzendörfer 23 Jun '18

23 Jun '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, June 24 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - hackathon outcome - test wafer structures - other stuff around libre silicon Happy to hear from you! David

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Mumble meeting
by David Lanzendörfer 18 Jun '18

18 Jun '18

Hello list Today no one at all joined the mumble conference... Please come next Sunday 9pm HKT, so that we can do a status check and coordination in the team and make sure we're on track for our road map. Cheers David

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