- Libresilicon-developers - libresilicon.com

Access and mask set (MOSIS <-> LibreSilicon )
by David Lanzendörfer 03 Aug '18

03 Aug '18

Hi all, hi Hagen Today I've received the RFID card for the lab, which means I can go in there whenever I want now :-) Following things have come up so far: a) We need additional pwell in the cell layouts, because we need to lift the potential/doping of the p-substrate and I wanna keep the higher resistance in the non active areas. Also the process contains a step for building in pwells so that in case someone wants to use n-substrate or undoped substrate, they can just change the doping parameters. b) I've now figured out how to map the layers from MOSIS to GDS2 so that we can build it with our process. For instance ptransistor and ntransistor are both included in both masks: The poly-mask together with polysilicon as well as the pimplant mask/nimplant mask. Also we will have to include the pdcontact within the pimplant mask. @Hagen: Can you add pwells into the standard cells? Then we can actually just use MOSIS and merge the layers accordingly to our process. I'm now fixing up some details about our process, like the Aluminum and isolation oxide layer thicknesses and then we can generate GDS2 files from your layout, upload the GDS2 to the web interface, pay the mask set and get started in the lab. Cheers David

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Reminder - next Mumble Session on July 29, 2018 21.00 HKT
by Hagen SANKOWSKI 29 Jul '18

29 Jul '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, July 29 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - test wafer status - other stuff around libre silicon Happy to hear from you! Hagen

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F.Y.I. - during the Tool Chain Hackathon in Dresden we talked about Rust
by Hagen SANKOWSKI 23 Jul '18

23 Jul '18

Hello. During the Tool Chain Hackathon in Dresden we talked also about Rust [0] as a Programming Language for our Design Software QtFlow [1]. Rust seems to be a nice, fast, promising, concurrent and safe language without an extra garbage collector. Well, as I am more a chip designer than a programmer I booked myself a Rust Course. Currently there are 4 participants - if you like (it is not free as in free beer) to learn Rust and the offer [2] fits to you - let's take the course together. Regards, Hagen. BTW, courses for Rust are very rare - I looked for one already more than two years. [0] https://en.wikipedia.org/wiki/Rust_(programming_language) [1] https://github.com/libresilicon/qtflow [2] https://www.linuxhotel.de/kurs/rust/ - 19.-21. November 18

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Pad cells on test wafer
by David Lanzendörfer 22 Jul '18

22 Jul '18

Hello Hagen Have you already an idea on how the design of our pad cells will look like? How many cascaded drivers stages will the cells contain? How many ESD rings will we provide in the padframe/cells? When I remember right we decided on an active driving capability of 10mA per cell as well as an open-collector option. At least my notes here say this :-) Cheers David

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Reminder - next Mumble Session on July 22, 2018 21.00 HKT
by Hagen SANKOWSKI 21 Jul '18

21 Jul '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, July 22 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - test wafer status - other stuff around libre silicon Happy to hear from you! Hagen

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Pearl River, demo board
by David Lanzendörfer 18 Jul '18

18 Jul '18

Hi Hagen, hi list Cedric and I just talked about the Pearl River test wafer, and I had an inspirational flash: We totally should make it possible to hook up LEDs to the output pads of the Pearl River on a PCB, so that we can demonstrate that the pad cell drivers have the capability of driving an LED! At the SEG plaza in Shenzhen there are many vendors with demo circuits showing the color and brightness of the LEDs in action. We could also make such a demo board in order to demonstrate the multiple different capabilities of the LibreSilicon process. Would do you think? Cheers David

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Some questions regarding the NVDLA and "NVIDIA Open NVDLA License and Agreement v1.0"
by Mohammad Amin Nili 18 Jul '18

18 Jul '18

Hello list, I’m not very much familiar with different types of licenses and their legal issues. So would some one do me a favor and answer my questions? 1. Is NVDLA a libre and royalty-free IP core? 2. Is it possible to modify it and relicense the modifications? 3. You know AFAIK the GPU architecture is somewhat similar to AI accelerator. So I’m thinking NVDLA is a good starting point but I don’t know about potential legal issues. So what do you think guys? Best regards, Manili NVDLA Official Website: http://nvdla.org/ <http://nvdla.org/> NVIDIA Open NVDLA License and Agreement v1.0: http://nvdla.org/license.html <http://nvdla.org/license.html>

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Reminder - next Mumble Session on July 14, 2018 21.00 HKT
by Hagen SANKOWSKI 15 Jul '18

15 Jul '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, July 15 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - test wafer status - other stuff around libre silicon Happy to hear from you! Hagen

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Diagram generation
by David Lanzendörfer 13 Jul '18

13 Jul '18

Hi folks I'm working here as a little side project on a way to generate wiring diagrams from the SoC configuration. -> https://github.com/libresilicon/fir2dot If someone would be interested to take over the project please ping me. The idea is to have nice block diagrams at the end of the day which can be used in documentations and data sheets and so on. Cheers David

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Reminder - next Mumble Session on July 8, 2018 21.00 HKT
by Hagen SANKOWSKI 12 Jul '18

12 Jul '18

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, July 8 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - current status - test wafer status - other stuff around libre silicon Happy to hear from you! Hagen

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